Last Chance for Tarfessock1 Features

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All that fits on a cardbus card?? :-)

What size, speed, and buswidth of the SDRAM? The ideal would be the largest RLDRAM-II device possible, but failing that, as large and fast as possible.

Any price estimates yet?

Regards, Tommy

Hi -

I don't know if anyone else has mentioned it, but please make sure you have lots of grounds, well spread out, on the external module connector(s).

Bob Perlman Cambrian Design Works

Web page with block diagram and outline spec is now on website here

John Adair Enterpo> We have mentioned Tarfessock1 before and now at the last point where we can

We think this all going to fit but certainly will be very tight. I will know more in few days when placement is more complete. SDRAM is likely to be DDR2 as we are using that on a number of boards but still not fully decided. DDR2 needs 2 more power supplies and hence board space. We make decision when we see how placement works out. Fallback position is SDRAM.

John Adair Enterpo> John Adair wrote:

Bob

Probably won't be as many as desireable but the option of using virual grounds using switched FPGA I/Os will be possible. I will also see if we can make any build options to hard ground what are I/O pins via solder bridge or 0201 resistor etc.

Generally we could use a few I/O than we have available on the 120 way connector currently pencilled in but the next size up standard connector is 180 way and is a bit big physically for the card edge. Generally we are trying to an internal standard for what might be developed as future products beyond Tarfessock1.

If we get a good response to this card it likely we will do a big brother version in Virtex-5 but that is only one of many projects competing for team time in Q4 and not guaranteed to happen as yet.

John Adair Enterpo> Hi -

Not enough grounds is a serious problem for good, high speed design. If there's a decent job done with differential routing for LVDS pairs (and LVDS voltage banks) then the demands on the grounds are lighter, allowing both a slow-speed, many I/O solution *and* a high-speed solution. The Spartan3E Starter kit had more than a dozen differential pairs but only about 4 pairs were "usable" because the others shared signals with LEDs or test headers that left huge stubs. If you did a good job with differential pairs, the speed might be pushed through the development connector.

All of our development boards support LVDS with matched pair routing. Even our low cost Raggedstone has about 50+ pairs of signals usually matched in length 1mm or less that run together from the relevant pair on the FPGA to the DIL headers. They don't share with other things generally either. This is part of the reason we use large I/O count devices even on our cheap boards. It is a major differentiation between our product and something like the Spartan-3 and 3E starter kits that use relatively small I/O count devices. We also tend use the large size package because of the SSO advantage and in fact we have an internal production test for some the boards with a very large percentage of I/O, at large toggle rate, running over our boards at 50Mhz and we get very good performance. Conversely we have seen other peoples designs that use PQFP and TQFP packages having very serious issues with small percentage toggle rates at relative low frequencies and the advantage of a BGA package is very large and well worth the little bit of extra money to have in most design cases.

Tarfessock1 will have support for LVDS built in a good percentage of the I/O if not all, I expect we will have 20+ pairs maybe even the lot to give 35 pairs. The grounding we will have to see how good it is and whether virtual grounds from FPGA I/Os are needed. However we do want to maintain the planned 70 I/O as it is fairly key to what we want to do outside the card itself. Ultimately whatever we do we won't please everyone and that is what market choice for. I do think we have formula that will win a lot of friends especially when the planned extended functionality becomes clearer in the shape of future add-on modules. I don't think the price is bad either especially if you qualify for student pricing but I'm sure someone will still point out the card costs more than it's constituent parts and designing it is cheap and not be equated in the price.

John Adair Enterpoint Ltd.

John_H wrote:

How about a programmable clock source? Even better, one which has equal / matched lines to each FPGA so both FPGAs get the same clock. Multiple independant frequencies would be better. This may also be a good selling point for universities, crossing a clock boundary is not trivial in most cases.

I've had passing interest in your offerings before - they look reasonable for the price and functionality offered. Your discussion about acute attention to differential I/O and use of BGA packages is making me think more seriously about shipping stuff across the pond. For Tarfessock1, I'm left wondering what needs to be developed by me versus what you would supply for CardBus access. I'm the FPGA guy, not into Windows drivers to save my life.

I'll take another, closer look at your site this weekend, particularly the info you've generated so far for Tarfessock1.

- John_H

It is a bit ironic but we actually probably ship more development boards to the US than within the UK. There is also a strange US tax situation such that our products are taxed lower than a US local company. A import tax called MFP does apply but is very small but I don't think Federal or State taxes get levied. If I'm wrong on that do tell me. We have spend many many hours talking and emailing various US bodies to try and get a definative answer without success.

Here in the UK our equivalent-ish VAT gets applyed to everything including our daily Digikey orders.

It is also worth saying that if you take the FEDEX option for carriage that in most cases you will get an order within 2 days. Occasionally customs will upset that schedule but this is a fairly low percentage and beyond our control to do anything about. The low cost carriage option we believe takes usually less than a week to get there if you go for that option.

When we release the product I don't expect everything will be as polished as desireable but we will try and get a level that is generally OK. The basic level that I will expect to launch with will be Device1(XC3S250E) looking a Parallel Port/Parallel Cable III supporting the bigger Device2(XC3S1200E). If we get the build right it should just be a Parallel Port to the OS and will pick up a driver automatically. Beyond that basic level we will be producing a software GUI etc. to access A/D, DAC etc but that needs some time to sort put and unlikely to available at launch.

John Adair Enterpo> I've had passing interest in your offerings before - they look reasonable

I will see what we can do. The physical size of a Cardbus card does not allow much room for an optimal placement to trace length match. We may also have problems finding enough board area too and I don't think double siding components is a serious option given the tight height restrictions.

At the 33Mhz the Cardbus notionally works at you would not have any issues using a common source clock of this frequency on any interface between the devices. Device1 is strictly limited in size and generally the intention is that most customers will not touch the shipping build programmed in. The through-put from Device2, via Device1 + Cardbus, to outside world will be limited by the Cardbus itself negating the need for a super fast interface between the devices. That all said we trying to support LVDS on the interface between the devices and a source synchronous approach will definately yield high bandwidth. I will be able to tell you more in a couple of weeks when the design will be pretty much fixed in schematic and layout placement.

John Adair Enterpo> "John Adair" wrote:

Any idea of a rough price on 5V9885? It looks useful although the jitter spec would not be good enough for high end applications. ICS8442 does a lot better in that respect.

John_H wrote: