Field-Programmable Gate Arrays

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chipscope opb monitor

I try to use the opb/iba unit of chipscope to monitor the opb bus within a simple edk design. I took the chipscope lab...
5 comments posted 20yrs
posted by someone
5 comments posted 20yrs posted by someone

ROM implementation

I have a 256x8 bit look up table in my vhdl design and I reach this look up table 64 times. I am using Synplify 8.6.1 t...
4 comments posted 20yrs
posted by etoktas
4 comments posted 20yrs posted by etoktas

ByteBlasterMV?

While looking for a circuit for an Altera ByteBlasterMV, I found this one for an original BB: The MV uses a 74HC244 ins...
2 comments posted 20yrs
posted by no
2 comments posted 20yrs posted by no

ANN: MicroBlaze simulator available

Hi after some while MicroBlaze uClinux ready simulator is again available http://www.xilant.com/downloads/xsim_1_0.zip...
0 comments posted 20yrs
posted by Antti.Lukats
0 comments posted 20yrs posted by Antti.Lukats

<EDK> PORT .... not found in MPD

hi I have problem when opening "old" project file, system.xmp, using XPS 6.3. It seems that "HW_VER" is not set up for...
1 comments posted 20yrs
posted by pasacco
1 comments posted 20yrs posted by pasacco

Delta sigma Modulator Interface

Hallo, I'm working on a interface for TI Delta Sigma Modulator. Following a guide I have developed a sinc^3 filter and...
0 comments posted 20yrs
posted by marc
0 comments posted 20yrs posted by marc

MGT RXPOLARITY setting

I have an Aurora core on a VII-Pro. I need to set the RXPOLARITY to 1. Where is this MGT signal controlled from? I thou...
0 comments posted 20yrs
posted by enquiries
0 comments posted 20yrs posted by enquiries

Trouble meeting EMAC RGMII timing in V4FX

Can I do anything (besides moving the pins around) to improve what you see below: =====================================...
0 comments posted 20yrs
posted by mbmsv
0 comments posted 20yrs posted by mbmsv

KASUMI source code in VHDL

Hi to all; Can anybody help me getting VHDL source code for KASUMI ? Thanks in advance for any help. Best regards. Adamo...
1 comments posted 20yrs
posted by adamou
1 comments posted 20yrs posted by adamou

Why 8 clock trees in Xilinx Spartan-3 device?

Synchronous design, in which all FFs are synchronized by a single clock, perhaps is the single most important methodolo...
10 comments posted 20yrs
posted by fpga002006
10 comments posted 20yrs posted by fpga002006

Using BUS'es in ISE WebPACK 3.3WP8.1 ???

Hi! I have a lot of PCB's with the XCR5064C CPLD on them, and would like to put them to use. I am forced to use old sof...
7 comments posted 20yrs
posted by per
7 comments posted 20yrs posted by per