I have a 256x8 bit look up table in my vhdl design and I reach this look up table 64 times.
I am using Synplify 8.6.1 to synthesize my code for ACTEL Ax or Proasic family and tool infers a lot of ROMs for this table.
As soon as I understand this inferred ROMs are made up of logic gates not reserved block Rams in the technology.
I heard that there is an attribute for Xilinx Virtex family named "select_ROM" in order to use block Rams instead of wasting logic gates of resources.
Is there any attribute for Actel family?
I would appreciate your help.