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ROM implementation

I have a 256x8 bit look up table in my vhdl design and I reach this look up table 64 times.

I am using Synplify 8.6.1 to synthesize my code for ACTEL Ax or Proasic family and tool infers a lot of ROMs for this table.

As soon as I understand this inferred ROMs are made up of logic gates not reserved block Rams in the technology.

I heard that there is an attribute for Xilinx Virtex family named "select_ROM" in order to use block Rams instead of wasting logic gates of resources.

Is there any attribute for Actel family?

I would appreciate your help.

Reply to
gollum
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Hi,

try the following:

signal ls_rom_out : std_logic_vector(... downto 0);

attribute syn_romstyle : string; attribute syn_romstyle of ls_rom_out : signal is "select_rom";

I do not know whether it can be applied with Actel devices ...

Rgds Andr=E9

Reply to
ALuPin

If you're using VHDL you might consider using LPM_ROM instead of however it is you've coded your table in the code. LPM is a standardized set of functions (Library of Parameterizable Modules...or something like that) that will make your code portable and totally avoid use of vendor specific attributes.

KJ

Reply to
KJ

Do Actel Block RAMs require registered reads (one clock delay from addr to data)? That may be your problem if your RTL does not mimic that behavior.

Andy

gollum wrote:

Reply to
Andy

I knew this attribute was for Xilinx only not Actel devices.

Thanx

snipped-for-privacy@web.de wrote:

Reply to
gollum

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