Can I do anything (besides moving the pins around) to improve what you see below:
============================================================================ ==== Timing constraint: TS_system_i_ll_temac_0_ll_temac_0_tx_gmii_mii_clk_in_i = PERIOD TIMEGRP
"system_i/ll_temac_0/ll_temac_0/tx_gmii_mii_clk_in_i" 8 ns HIGH 50%;
20 items analyzed, 2 timing errors detected. (2 setup errors, 0 hold errors) Minimum period is 8.290ns.----------------------------------------------------------------------------
---- Slack: -0.145ns (requirement - (data path - clock path skew
- uncertainty)) Source: system_i/ll_temac_0/ll_temac_0/temac_0/v4_emac (CPU) Destination: system_i/ll_temac_0/ll_temac_0/rgmii0/txd_falling_i_2 (FF) Requirement: 4.000ns Data Path Delay: 3.881ns (Levels of Logic = 0) Clock Path Skew: -0.123ns Source Clock: RGMII_TXC_0 rising at 0.000ns Destination Clock: RGMII_TXC_0 falling at 4.000ns Clock Uncertainty: 0.141ns
Data Path: system_i/ll_temac_0/ll_temac_0/temac_0/v4_emac to system_i/ll_temac_0/ll_temac_0/rgmii0/txd_falling_i_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- EMAC_X0Y1.EMAC0PHYTXD6 Tmaccko_TXD 2.827 system_i/ll_temac_0/ll_temac_0/temac_0/v4_emac
system_i/ll_temac_0/ll_temac_0/temac_0/v4_emac SLICE_X19Y153.BY net (fanout=1) 0.712 system_i/ll_temac_0/ll_temac_0/rgmii_txd_falling_i SLICE_X19Y153.CLK Tdick 0.342 system_i/ll_temac_0/ll_temac_0/rgmii0/txd_falling_i
system_i/ll_temac_0/ll_temac_0/rgmii0/txd_falling_i_2 --------------------------------------------------- -------------------
-------- Total 3.881ns (3.169ns logic,
0.712ns route) (81.7% logic, 18.3% route)Thanks, /Mikhail