Field-Programmable Gate Arrays

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verilog versus vhdl

Hi Group I have to implement a design which requires an FPGA, but to do so among other things I obviousely first have t...
48 comments posted 20yrs
posted by m.zingg
48 comments posted 20yrs posted by m.zingg

Post PAR simulation, type not match

Hi During loading for post route simulation (modelsim_SE, ISE7.1), following errors occurred. The design block contains...
0 comments posted 20yrs
posted by pasacco
0 comments posted 20yrs posted by pasacco

virtex ppclinux files

Hi I have uploaded the files once available from Pauls website at the university in Australia http://hydraxc.xilant.com...
2 comments posted 20yrs
posted by Antti.Lukats
2 comments posted 20yrs posted by Antti.Lukats

checking the FFT cores on Xilinx FPGAs

Hi, I am using a FFT core block on Xilinx Virtex-4 FPGA. On simulating a 1024 point FFT with a 64 bit 10 MHz PRBS, I se...
0 comments posted 20yrs
posted by vivek.menon79
0 comments posted 20yrs posted by vivek.menon79

Synplify

I have took a Xilinx design through synplify and then started ise fro synplify to place and route. The problem is I hav...
2 comments posted 20yrs
posted by maxascent
2 comments posted 20yrs posted by maxascent

Noob quesion about SDRAM usage.

Hello, I'm relatively new to FPGA programming and looking for some advice. I have an application that needs reliable, h...
2 comments posted 20yrs
posted by drs39
2 comments posted 20yrs posted by drs39

DDR Controller

Hi, I am to build a fpga system that captures data from external signals and store it to DDR, also after the capture da...
4 comments posted 20yrs
posted by yy7d6
4 comments posted 20yrs posted by yy7d6

Raggedstone1 ADV7202 Module

These are finally in stock for those who have been after them. John Adair Enterpoint Ltd.
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

Xilinx PCI Core burst problem

Hello, I have designed a CardBus Design, which is very similar to pci with full master functionality. The main aim of t...
4 comments posted 20yrs
posted by info
4 comments posted 20yrs posted by info

profiling my application in microblaze...

Hi guys, I'm trying to profile my application while it is running on microblaze. However I have a problem in setting pr...
1 comments posted 20yrs
posted by amirhossein.gholamipour
1 comments posted 20yrs posted by amirhossein.gholamipour

RocketIO simulation in VCS

I am trying to simulate RocketIO MGT in VCS. When I do vcs -lmc-swift-template GT_SWIFT it says it couldn't find libswi...
3 comments posted 20yrs
posted by sovan.kundu
3 comments posted 20yrs posted by sovan.kundu

Xilinx System Generator crashes repeatedly

I am sorry for posting this as I have already posted it on the comp.soft-sys.matlab. I have a MatLab 7.2/Simulink 6.4/X...
3 comments posted 20yrs
posted by mmkhajah
3 comments posted 20yrs posted by mmkhajah

Microblaze Sierro RTOS is no longer available??

Xilinx website still has links to it http://www.realfast.se/RFIPP/HWSW/system/system.shtml but all reference to the Sier...
2 comments posted 20yrs
posted by Antti.Lukats
2 comments posted 20yrs posted by Antti.Lukats

Cyclone I & II memory fmax

Hi group, using a 128x32 bit simple dual port memory with independent read and write clock results in following fmax fo...
6 comments posted 20yrs
posted by mschoebe
6 comments posted 20yrs posted by mschoebe