I have took a Xilinx design through synplify and then started ise fro synplify to place and route. The problem is I have some coregen component and when I try and place and route it complains about missing edif files. can find these files in the synplify directory but how do I tell ise abou them?
Cheers
Jon
In the Xilinx ISE GUI, right-click on Implementation or Translate in the Processes window, the Translate Properties include a "Macro Search Path" where you can browse-to and specify the directory that holds any extra edif or nco files.
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