Noob quesion about SDRAM usage.

Hello,

I'm relatively new to FPGA programming and looking for some advice. I have an application that needs reliable, high bandwidth (+50 MHz), access to a few Megs worth of RAM and I am wondering how I should go about this.

I am working with the Xilinx ML403 development board which has the Virtex-4 FX12 FPGA and 64 MB of DDR SDRAM. My intention is to implement my project as a peripheral component of a processor system generated by EDK. The three possible ways I have come up with for implementing this part of my project are:

  1. Use the EDK memory controller core as a separate peripheral on the PLB and have a software application to transfer data between it and my peripheral. This seems to be the easiest option to implement but I doubt that it will give me the performance I need. Also it will tie up the processor.

  1. As before I could use the EDK memory controller core as a separate peripheral on the PLB however this time I could implement my peripheral as a master on the PLB bus. I believe that this would allow my peripheral to directly access the SDRAM controller without interference of/with the processor. However I do not know how difficult it is to write a PLB bus master and I do not know how to predict how detrimental other traffic on the PLB bus will be to the available bandwidth for my application.

  2. Finally I could integrate the SDRAM controller into my peripheral. This clearly would be the highest bandwidth solution, however it seems the most technically complicated.

As I mentioned I am a relative beginner with FPGA programming and am looking for advice on how to proceed. I would also greatly appreciate any links to example projects or documentation that might be relevant to this project.

Thanks in advance for the help!

Regards,

-Dan

Reply to
drs39
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Bandwidth is measured in bits/s or bytes/s. How much are you storing each cycle?

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To me this is the "obvious" right way to go unless you're really pushing things to the edge (which will require special tricks with DDR). Rest assured, writing a PLB master is way way easier than writing a DDR SDRAM controller (admitted I have no experience with PLB, but otherwise there would be something very wrong with the PLB design!).

Methinks that this is not likely to be the best way to get started with FPGAs. You may start with a few simpler projects first, followed by a few simple PLB peripherals. Otherwise you'll spend a lot of time in frustration.

Tommy

Reply to
Tommy Thorn

Hello Tommy,

Thanks for the advice and terminology correction. 50 MHz is the rate that I would like be able to retrieve bit patterns stored in the SDRAM. So I should have put my specification at 1 GB/s (I need to get 20 Bit patterns at 50 MHz).

I'll focus on trying to implement the connection over the PLB bus. I understand that this is not the ideal way to start out with FPGAs. Unfortunately though I need the FPGA, and in particular this memory link for my research work so I can't choose an easier project. By now though, as a grad student, I am very used to frustrating learning curves. Thanks again though for helping me choose the easier route to deal with this problem.

cheers,

-Dan

Tommy Thorn wrote:

Reply to
drs39

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