Hello,
I'm relatively new to FPGA programming and looking for some advice. I have an application that needs reliable, high bandwidth (+50 MHz), access to a few Megs worth of RAM and I am wondering how I should go about this.
I am working with the Xilinx ML403 development board which has the Virtex-4 FX12 FPGA and 64 MB of DDR SDRAM. My intention is to implement my project as a peripheral component of a processor system generated by EDK. The three possible ways I have come up with for implementing this part of my project are:
- Use the EDK memory controller core as a separate peripheral on the PLB and have a software application to transfer data between it and my peripheral. This seems to be the easiest option to implement but I doubt that it will give me the performance I need. Also it will tie up the processor.
- As before I could use the EDK memory controller core as a separate peripheral on the PLB however this time I could implement my peripheral as a master on the PLB bus. I believe that this would allow my peripheral to directly access the SDRAM controller without interference of/with the processor. However I do not know how difficult it is to write a PLB bus master and I do not know how to predict how detrimental other traffic on the PLB bus will be to the available bandwidth for my application.
- Finally I could integrate the SDRAM controller into my peripheral. This clearly would be the highest bandwidth solution, however it seems the most technically complicated.
As I mentioned I am a relative beginner with FPGA programming and am looking for advice on how to proceed. I would also greatly appreciate any links to example projects or documentation that might be relevant to this project.
Thanks in advance for the help!
Regards,
-Dan