Component Instantiation ERROR:HDLParsers:3281 in ISE 8.1i

I receive the following error:

ERROR:HDLParsers:3281 - "C:/Work/Hdl/dsp/qrdc.vhd" Line 89. rtl_ar is not an architecture body for counterup in library work.

Wrong! "rtl_ar" IS an architecture body stupid ISE!

Here is line 89:

count_ins : entity work.counterup(rtl_ar) generic map ( dwidth_g => CNT_WIDTH_C, cntinit_g => 0 ) port map ( clk => clk, rst_n_a => rst_n_a, en => cnt_en, clr => cnt_clr, q => cnt_q );

I am able to compile qrdc.vhd under synthesis/implementation, but it fails when I try to compile my test-bench "qrdc_tb.vhd" under ISE simulator.

Any ideas? Note, all of the files are in my working library, but from various directories, above and below my project root (i.e. "../dsp/qrdc.vhd").

Thanks,

-B