Hi
During loading for post route simulation (modelsim_SE, ISE7.1), following errors occurred. The design block contains "lots of" ports (which is more than 300). So what I did was I implemented after uncheking "Trim unconnected signals" and checking "Create I/O Pads for Ports". In UCF file, I connected clock and reset pins only.
It seems that the I/O of design module and test bench are not matching. I checked NCD file using FPGA editor and it is (seems) quite okay.
Does anyone have this experience? thankyou again in advance
---------------------------------------------------------------------------------------------------------- # Loading work.pe(structure) # ** Failure: (vsim-3807) Types do not match between component and entity for port rd_data_i # Time: 0 ns Iteration: 0 Instance: /pe_tb/top File: # Loading C:/Modeltech_6.1c/Compxlib/simprim.x_tri_pp(x_tri_pp_v) # Loading C:/Modeltech_6.1c/Compxlib/simprim.x_inv_pp(x_inv_pp_v) # Fatal error at c:/Xilinx/vhdl/src/simprims/simprim_VITAL_mti.vhd line
109182 # while elaborating region: /pe_tb/top/rd_data_0_13_obuf # Load interrupted---------------------------------------------------------------------------------------------------------