Field-Programmable Gate Arrays

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Xilinx ISE 8.2 implementation problem

Hi, I'm using ISE 8.2.01i and Synplify 8.6.1 as synthesis tool. For one of my project, I can synthesize but when I try...
1 comments posted 20yrs
posted by matthieu.cattin
1 comments posted 20yrs posted by matthieu.cattin

coming soon: MB 5.0

http://xilant.com/content/view/45/2/ soon... Antti
1 comments posted 20yrs
posted by Antti.Lukats
1 comments posted 20yrs posted by Antti.Lukats

Coregen help

Hi all, I am using the FFT coregen block with pipelined streaming option in my design implementation on a Virtex-4 FPGA...
6 comments posted 20yrs
posted by vivek.menon79
6 comments posted 20yrs posted by vivek.menon79

EDK, user IP, how to use user-functions

hi In EDK, I am having problem with managing user functions in user IP component. The error message is that -----------...
1 comments posted 20yrs
posted by pasacco
1 comments posted 20yrs posted by pasacco

ASIC Design Engineer Job in SHENZHEN China

We are a leading IC design company in China, and mainly supply LCD Driver LCD. Now we supply the following positions to...
1 comments posted 20yrs
posted by dandan_h
1 comments posted 20yrs posted by dandan_h

How can we fully utilize available BRAMs...

Hi guys, I have a problem with how EDK utilizes BRAMs for data and instruction LMB memories. I have 64KB instruction an...
5 comments posted 20yrs
posted by amirhossein.gholamipour
5 comments posted 20yrs posted by amirhossein.gholamipour

MicroBlaze SPI interrupts

Hello All, I'm on a project which has ballooned in scope such that it calls for implementing the MicroBlaze (originally...
1 comments posted 20yrs
posted by fbs.consulting
1 comments posted 20yrs posted by fbs.consulting

generating sine-like waveforms

hello everybody, are there any _simple_ ways of generating a sine waveform, maybe from a reference pulse/saw/triangle s...
21 comments posted 20yrs
posted by burn.sir
21 comments posted 20yrs posted by burn.sir

USB application on ML40X boards

Hi, I'm a beginner in FPGA development and I am trying to develop an image processing application on a Xilinx ml403 dev...
0 comments posted 20yrs
posted by elepardu
0 comments posted 20yrs posted by elepardu

MPD file option HDL

I have an IP core made up of verilog files as well as vhdl files. How do I set my mpd file for the bitstream generation...
3 comments posted 20yrs
posted by nitesh.guinde
3 comments posted 20yrs posted by nitesh.guinde

Virtex-4 RocketIO

Dear all, I'm in the early stages of designing a board with a Virtex-4 FX on it which we are planning to use for develo...
2 comments posted 20yrs
posted by petermendham
2 comments posted 20yrs posted by petermendham

ISE8.2 + .ngo file + Leonardo

Hi, I have a ISE7.1 project containing the PCI .ngo file. This completes correctly. Ugrading to ISE8.2i the .tcl script...
2 comments posted 20yrs
posted by
2 comments posted 20yrs posted by

Chipscope

Hi I am using the eval version of chipscope 8.2 with a Virtex 2 Pro. I have problem when I configure the FPGA I get the...
5 comments posted 20yrs
posted by maxascent
5 comments posted 20yrs posted by maxascent