Field-Programmable Gate Arrays

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Real-world soft-cpu performance

Hi all, So, before I splash out on the EDK, I'd really appreciate some advice on what the real MHz limits are on the mi...
7 comments posted 20yrs
posted by simon.gornall
7 comments posted 20yrs posted by simon.gornall

xst synthesis with attributes failure

I have the following code which errors in 8.1.3 sw : the error is something like ..actual value associated with a gener...
3 comments posted 20yrs
posted by mikej
3 comments posted 20yrs posted by mikej

Development Board Offers

For all our loyal customers we are running a set of one week offers for August. First one out is the Raggedstone1 RS1-4...
0 comments posted 20yrs
posted by g1
0 comments posted 20yrs posted by g1

Unpicking Logical Synthesis

Hiya group, I've got a design that is contained within a single VHDL file. It instantiates a component that is in an NG...
3 comments posted 20yrs
posted by robin.bruce
3 comments posted 20yrs posted by robin.bruce

Xilinx PCI Core & CardBus

Hi everybody, I have designed a Cardbus Card with Spartan 3 and Xilinx PCI Core, which works very well in all kind of n...
4 comments posted 20yrs
posted by info
4 comments posted 20yrs posted by info

DSP core, use of real type signals (Altera Stratix)

Hello, I have a little problem, it is about real values in VHDL, and the way = Quartus is managing them. I am describin...
1 comments posted 20yrs
posted by Erik.Verhagen
1 comments posted 20yrs posted by Erik.Verhagen

ISE software bug???

Hi, I'm confused over two days for the sollution of the next problem: environment: software : WP8.1.03i & WP8.2.01i (tr...
18 comments posted 20yrs
posted by bit_vector
18 comments posted 20yrs posted by bit_vector

A Newbie question

Hi Everybody, I am just starting with the Xilinx Multimedia Board (Virtex II). I have written a trivial verilog program...
4 comments posted 20yrs
posted by thisissantanu
4 comments posted 20yrs posted by thisissantanu

Newcomer question

Hi there, I am doing my first FPGA/VHDL design. Previously I did CPLD designs utilizing Altera's AHDL. I coded the VHDL...
1 comments posted 20yrs
posted by johannes.hausensteiner
1 comments posted 20yrs posted by johannes.hausensteiner

Simple code to check out Spartan3 starter kit?

I've got ISE 8.1 running under Linux (Gentoo, 2.6.15 kernel, amd64 - I plan to use the xc3sprog program to send the bit...
4 comments posted 20yrs
posted by ptkwt
4 comments posted 20yrs posted by ptkwt

Spartan 3 StarterKit Weirdness

I'm experiencing something strange with my Spartan 3 starter kit. It seems that when I download a bitstream via jtag di...
3 comments posted 20yrs
posted by david-removeme-carne
3 comments posted 20yrs posted by david-removeme-carne

Question about SSTL

I'm about to test a DDR2-SDRAM controller. I have a question regarding the use of SSTL IO standard in Virtex-4: Is it n...
1 comments posted 20yrs
posted by taileb.mehdi
1 comments posted 20yrs posted by taileb.mehdi

Avnet V2Pro dev board "Hello world"

Hi, I'm trying to get started with logic programming on this board (ADS-XLX-V2PRO-DEVP20-6), ie. VHDL and no processors...
4 comments posted 20yrs
posted by iliev
4 comments posted 20yrs posted by iliev

100 Mbit manchester coded signal in FPGA

Hi all, we are trying to implement a 100 MBit communication link witch uses manchester coding. The signal is generated...
37 comments posted 20yrs
posted by michaeldre
37 comments posted 20yrs posted by michaeldre