Latest threads in Field-Programmable Gate Arrays

Switching two (synchronous) clocks with variable phase difference, without glitching or period loss

I have two clocks which are relatively synchronous (ie. the frequencies are exactly the same because the originate from...

10 20yrs

peter

10 20yrs peter

Real-world soft-cpu performance

Hi all, So, before I splash out on the EDK, I'd really appreciate some advice on what the real MHz limits are on the mi...

7 20yrs

simon.gornall

7 20yrs simon.gornall

xst synthesis with attributes failure

I have the following code which errors in 8.1.3 sw : the error is something like ..actual value associated with a gener...

3 20yrs

mikej

3 20yrs mikej

Development Board Offers

For all our loyal customers we are running a set of one week offers for August. First one out is the Raggedstone1 RS1-4...

0 20yrs

g1

0 20yrs g1

Unpicking Logical Synthesis

Hiya group, I've got a design that is contained within a single VHDL file. It instantiates a component that is in an NG...

3 20yrs

robin.bruce

3 20yrs robin.bruce

Xilinx PCI Core & CardBus

Hi everybody, I have designed a Cardbus Card with Spartan 3 and Xilinx PCI Core, which works very well in all kind of n...

4 20yrs

info

4 20yrs info

DSP core, use of real type signals (Altera Stratix)

Hello, I have a little problem, it is about real values in VHDL, and the way = Quartus is managing them. I am describin...

1 20yrs

Erik.Verhagen

1 20yrs Erik.Verhagen

ISE software bug???

Hi, I'm confused over two days for the sollution of the next problem: environment: software : WP8.1.03i & WP8.2.01i (tr...

18 20yrs

bit_vector

18 20yrs bit_vector

A Newbie question

Hi Everybody, I am just starting with the Xilinx Multimedia Board (Virtex II). I have written a trivial verilog program...

4 20yrs

thisissantanu

4 20yrs thisissantanu

Newcomer question

Hi there, I am doing my first FPGA/VHDL design. Previously I did CPLD designs utilizing Altera's AHDL. I coded the VHDL...

1 20yrs

johannes.hausensteiner

1 20yrs johannes.hausensteiner

Simple code to check out Spartan3 starter kit?

I've got ISE 8.1 running under Linux (Gentoo, 2.6.15 kernel, amd64 - I plan to use the xc3sprog program to send the bit...

4 20yrs

ptkwt

4 20yrs ptkwt

Spartan 3 StarterKit Weirdness

I'm experiencing something strange with my Spartan 3 starter kit. It seems that when I download a bitstream via jtag di...

3 20yrs

david-removeme-carne

3 20yrs david-removeme-carne

Question about SSTL

I'm about to test a DDR2-SDRAM controller. I have a question regarding the use of SSTL IO standard in Virtex-4: Is it n...

1 20yrs

taileb.mehdi

1 20yrs taileb.mehdi

Avnet V2Pro dev board "Hello world"

Hi, I'm trying to get started with logic programming on this board (ADS-XLX-V2PRO-DEVP20-6), ie. VHDL and no processors...

4 20yrs

iliev

4 20yrs iliev

logic analyzer for Spartan3 starterkit, GPL VHDL and java based sw

http://www.sump.org/projects/analyzer/ (link info with thanks to Carsten) Antti

2 20yrs

antti

2 20yrs antti

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