Hi Everybody,
I am just starting with the Xilinx Multimedia Board (Virtex II).
I have written a trivial verilog program using ISE 6.3:
------------------------------------- module mult(c_upper, c_lower); output [31:0] c_upper; output [31:0] c_lower;
reg [31:0] ia; reg [31:0] ib; reg [63:0] c;
initial begin ia=32'h10000001; ib=32'h00000002; c=ia*ib; end
assign c_lower=c[31:0]; assign c_upper=c[63:32];
endmodule
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As for assigning pins, I have used BANK0 for storing the c_upper and c_lower.
The program compiled fine, and the bitstream was generated and downloaded successfully. But the problem is now, how do I see the memory where the result is supposed to be present?
It is possible that I am asking a stupid question, but at our place, nobody has any experience with this board, and I am having to figure this out on my own.
I would be grateful if you could point me to any suitable document that might answer my question, or provide a solution.
Thaks in advance.
-Santanu Chatterjee