A Newbie question

Aug 09, 2006 4 Replies
S

Hi Everybody,



I am just starting with the Xilinx Multimedia Board (Virtex II).



I have written a trivial verilog program using ISE 6.3:



------------------------------------- module mult(c_upper, c_lower); output [31:0] c_upper; output [31:0] c_lower;



reg [31:0] ia; reg [31:0] ib; reg [63:0] c;



initial begin ia=32'h10000001; ib=32'h00000002; c=ia*ib; end



assign c_lower=c[31:0]; assign c_upper=c[63:32];



endmodule



---------------------------------------



As for assigning pins, I have used BANK0 for storing the c_upper and c_lower.



The program compiled fine, and the bitstream was generated and downloaded successfully. But the problem is now, how do I see the memory where the result is supposed to be present?



It is possible that I am asking a stupid question, but at our place, nobody has any experience with this board, and I am having to figure this out on my own.



I would be grateful if you could point me to any suitable document that might answer my question, or provide a solution.



Thaks in advance.


-Santanu Chatterjee



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M

Either run a simulation or put a probe on the c_lower pins.

-- Mike Treseler

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T

I think he needs more help than that.

Santanu, only a subset of Verilog is synthesizable. Initial contructs in particular have no meaning for synthesis and your example is pretty nearly a no-op.

Tommy

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S

First of all, thank you both for replying.

Mike, did you mean a logic analyser probe? If so, we don't have a logic analyser here as yet. Simulation is not a problem, but I wanted to see the whether the results were actually stored in the memory.

Tommy, as you said, if the initial construct is non synthesizable, then how is a pin set to a default value using verilog? In any case, isn't the memory location supposed to store the multiplication result?

In trivial cases, I can see the results by means of turning the two LEDs on or off, but for a 64 bit multiplied value, apparently I have no other way to see the result, other than storing it in memory and reading it in some way, since this board (the Xilinx Virtex II based Microblaze and Multimedia Demonstration Board) has no GPIO pins. There are audio, video, ethernet, rs232 ports, but they require respective controllers to access them, which I am currently not in a position to write. I was trying to use the rs232 code from

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but I could not get it working as yet, especially since they use a 'wishbone' interface, which I know nothing about.

Regards, Santanu

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B

Some devices allow you to assign default/startup values to registers. It can be done for Altera parts through assignment editor. A common alternative (and i think generally accepted as better) approach is to have a reset signal, which triggers an "always" block. i.e.

module somemodule(... rst, ..., outA ...) ... output [31:0] outA; reg [31:0] out_regA; ... always @(posedge rst) begin out_regA

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