Hiya group,
I've got a design that is contained within a single VHDL file. It instantiates a component that is in an NGC format, so I have two files in my ISE project, one VHDL and one NGC. What I would like to be able to do is synthesise both to a single NGC by passing through the logical synthesis stage in ISE (XST). I'd like to get the estimated combined resource use and clock rate this way, and have a single logical netlist for the design to export it. Is there any easy way to do this?
== tin-foil hat on == Is there anyway to return to VHDL from the NGC stage (even via EDIF)? == tin-foil hat off ==
Thanks,
Robin