Hi there,
I am doing my first FPGA/VHDL design. Previously I did CPLD designs utilizing Altera's AHDL. I coded the VHDL source files and simulated it successfully with Modelsim. Then I made the I/O pin assignments and made the .bit file and loaded it to the FPGA. To my disappointment only some of the signals are correct; the functionality of the system does not work. I am using ispLEVER and a Lattice LFEC33 FPGA. There is a "Post Place and Route Simulation" action available within ispLEVER (actually it starts Modelsim), but this does not work. Modelsim always complains "Error loading design". What possibilities do I have to debug my design?
Thanks a lot,
Johannes