Field-Programmable Gate Arrays

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100 Mbit manchester coded signal in FPGA

Hi all, we are trying to implement a 100 MBit communication link witch uses manchester coding. The signal is generated...
37 comments posted 20yrs
posted by michaeldre
37 comments posted 20yrs posted by michaeldre

Networking : Multicast Performance

Hello all, I am working with the Xilinx ML403 board and I am trying to find some documentation about the UDP Multicast p...
1 comments posted 20yrs
posted by jpriceelvis.removeme
1 comments posted 20yrs posted by jpriceelvis.removeme

Switching speeds on V4FX RocketIO

Has anyone been able to dynamically switch speeds on the V4FX RocketIO?. I've been trying to switch between 2.5GHz and...
0 comments posted 20yrs
posted by bjrosen
0 comments posted 20yrs posted by bjrosen

New to RocketIO

Dear all, I'm new to RocketIO and would appreciate any guidance from a hw design perspective. I am currently doing sche...
0 comments posted 20yrs
posted by petermendham
0 comments posted 20yrs posted by petermendham

Who is your favourite FPGA guru?

Hi all, I was just pondering the idea of "gurus" & I thought the following questions may hopefully make some interestin...
15 comments posted 20yrs
posted by tony
15 comments posted 20yrs posted by tony

3.3V configuration of Spartan-3?

I've got a Spartan-3 which is configured (in master serial mode) from an XCF04S, and which is also in a JTAG chain whic...
3 comments posted 20yrs
posted by eml
3 comments posted 20yrs posted by eml

WHAT SITUATION I NEED A BUFFER

I am a newer for FPGA. I am reading some vhdl codes of others. I find they often use some buffers in design, such as IB...
13 comments posted 20yrs
posted by threeinchnail
13 comments posted 20yrs posted by threeinchnail

FPGA : PCI-Xilinx Core, PC not booting

Hello all, We have made a PCI board using Xilinx PCI core. with master and target capabilities. It works well with inte...
6 comments posted 20yrs
posted by pbijoy
6 comments posted 20yrs posted by pbijoy

How do I treat "default" case which is useless?

I need to use only 5 out of the 8 cases, but for completeness's sake, a default case is needed in order to avoid unwant...
17 comments posted 20yrs
posted by Mr. Ken
17 comments posted 20yrs posted by Mr. Ken

Changing SerDes speed on the V4FX RocketIO

Has anyone been able to dynamically change the SerDes speed on the V4FX RocketIO. I've been able to get the RocketIO to...
0 comments posted 20yrs
posted by bjrosen
0 comments posted 20yrs posted by bjrosen

clock problems with Spartan 3E starter kit

I'm trying to use the ethernet controller on my starter kit. This chip generates a 25 MHz clock and with every rising e...
1 comments posted 20yrs
posted by fb
1 comments posted 20yrs posted by fb

Xilinx Impact USB speed problem

Starting with ISE Webpack 8.2, I have to manually set the speed of the USB port to 3 MHz every time I start Impact, bec...
1 comments posted 20yrs
posted by fb
1 comments posted 20yrs posted by fb

FPGA interface to serial ADC

I'm trying to get an FPGA (Spartan-II) to communicate with an ADC (Serial interface, with a maximum throughput rate of...
5 comments posted 20yrs
posted by kyomubi_ki
5 comments posted 20yrs posted by kyomubi_ki