Field-Programmable Gate Arrays

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Gaisler on a Spartan 3E Starter Kit?

Gaisler has a nice suite of GPL'd IP for an AMBA-bussed Leon3 (SPARC) system with Ethernet, DDR RAM, Spacewire, PCI, AE...
6 comments posted 20yrs
posted by dmpalmer
6 comments posted 20yrs posted by dmpalmer

Clock domain crossing (again)

Hey guys, I'm having trouble getting started with my first clock-domain crossing task. I need to take in 2 signals; a 2...
9 comments posted 20yrs
posted by jai.dhar
9 comments posted 20yrs posted by jai.dhar

EDK: OPB_IPIF, too many versions...

Hi all, I have created a custom OPB peripheral template with the wizard and now trying to make sense of it... I noticed...
5 comments posted 20yrs
posted by mbmsv
5 comments posted 20yrs posted by mbmsv

Dio5 interface with ps2 port

Hi, I am trying to interface a keyboard with the Xilinx Dio5 board ps2 port using EDK(c dev kit). From my understanding...
3 comments posted 20yrs
posted by dont.smoke
3 comments posted 20yrs posted by dont.smoke

Embedded clocks

I was posting to the thread on the embedded clock in a Manchester encoded bit stream and realized that the clock is not...
43 comments posted 20yrs
posted by spamgoeshere4
43 comments posted 20yrs posted by spamgoeshere4

Invoking Cadence NC Sim within Xilinx ISE

Hello, Could someone here explain how to do the above. I have been regularly using only the Modelsim MXE versions for X...
1 comments posted 20yrs
posted by anil.janumpally
1 comments posted 20yrs posted by anil.janumpally

consistancy in synthesis/ simulation model

Hi, This is regarding synthesis of code on ISE 7. II have a design that I want to run on spartan 3, 400K gate FPGA. It...
5 comments posted 20yrs
posted by bj.srikanth
5 comments posted 20yrs posted by bj.srikanth

Compiler can't detect std_logic_1164 package

Hello. Newbie here. I am trying to write a very simple program to simulate a multiplexer. I am using the xilinx version...
7 comments posted 20yrs
posted by aijazbaig1
7 comments posted 20yrs posted by aijazbaig1

NgdBuild:604 error

Hi, I'm tearing my hair out and I can't find the answer to this in any of the Xilinx solutions!!! ---8
9 comments posted 20yrs
posted by markm
9 comments posted 20yrs posted by markm

Anyone really using Virtex-5 FPGAs yet?

Which parts? How long was delivery? What is the cost? What development/OEM boards are available?
0 comments posted 20yrs
posted by pomerado
0 comments posted 20yrs posted by pomerado

Altera SOPC ModelSim question

I'm trying to construct a SOPC component of JOP [1]. As it did not work in the FPGA on the first try (of course) I woul...
2 comments posted 20yrs
posted by mschoebe
2 comments posted 20yrs posted by mschoebe

TIG on Xilinx Asynch FIFO?

I am having a hard time getting ISE/XST to ignore clock skew between two clock domains from an asychronous FIFO generat...
4 comments posted 20yrs
posted by killerhertz
4 comments posted 20yrs posted by killerhertz

EDK peripherals and CoreGen netlists

Hi all, I am building EDK peripheral with FIFO Coregen 2.3 included. In ISE peripheral project everything is working fi...
3 comments posted 20yrs
posted by ales.gorkic
3 comments posted 20yrs posted by ales.gorkic