Hello,
Could someone here explain how to do the above. I have been regularly using only the Modelsim MXE versions for Xilinx ISE and invoking the simulation was very easy because it was done through the GUI.
But my gatelevel simulations run very slow and i want use Cadence NcSim for that. I am not very friendly with NcSim and therefore would request some one to guide me how to proceed in a very simple way.
Thanks in advance.
Regards, Anil
Anil, I've not done this within ISE framework, but pretty much only on Linux m/c. It is very straightforward:
ncverilog -f flist
With "flist" being a file with a list of your source (Verilog) files. I personally am more favourite of a 3-step process - ncvlog/ncelab/ncsim - but this should get you started. Feel free to write to: tech_help noveldv.com for more.If we find time we will help you.
Regards Ajeetha, CVC
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