I am building EDK peripheral with FIFO Coregen 2.3 included. In ISE peripheral project everything is working fine (FIFO netlist is included and properly sinthesized and built), but in EDK flow every time i get an error during bulid: "unresolved FIFO - missing netlist or pin misspeling can cause this..."
I have of course included in MPD: OPTION IMP_NETLIST = TRUE OPTION STYLE = MIX OPTION RUN_NGCBUILD = TRUE
and in BDD file: Files async_fifo.edn async_fifo_fifo_generator_v2_3_fifo16_1.edn
and in PAO FIFO wrapper: lib peripheral_v1_00_a async_fifo vhdl
but the problem persists (and eating my nerves :( ). Files are not properly copied (included) to project implementation directory. I managed to resolve the problem by manually copying netlists to the imp directory, but that is not what I want.
My methodology obviously doesn't work. Does anyone knows the proper procedure to fix this (or is maybe willing to give an example)?