EDK peripherals and CoreGen netlists

Guru 19 years ago

Hi all,

I am building EDK peripheral with FIFO Coregen 2.3 included. In ISE peripheral project everything is working fine (FIFO netlist is included and properly sinthesized and built), but in EDK flow every time i get an error during bulid: "unresolved FIFO - missing netlist or pin misspeling can cause this..."

I have of course included in MPD: OPTION IMP_NETLIST = TRUE OPTION STYLE = MIX OPTION RUN_NGCBUILD = TRUE

and in BDD file: Files async_fifo.edn async_fifo_fifo_generator_v2_3_fifo16_1.edn

and in PAO FIFO wrapper: lib peripheral_v1_00_a async_fifo vhdl

but the problem persists (and eating my nerves :( ). Files are not properly copied (included) to project implementation directory. I managed to resolve the problem by manually copying netlists to the imp directory, but that is not what I want.

My methodology obviously doesn't work. Does anyone knows the proper procedure to fix this (or is maybe willing to give an example)?

Cheers,

Guru

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Johan Bernspång 19 years ago

Every time I create a new EDK peripheral which includes cores from Coregen it seem to be a struggle to get the ngdbuild tool to find the cores. The only think I can think of is that your netlist-catalog is either misspelled or that your bbd file has the extension bdd (as you have written in your post). If that is not the case you can try to put the netlist names on one line as below.

Files async_fifo.edn, async_fifo_fifo_generator_v2_3_fifo16_1.edn

Regards

----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------

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MM 19 years ago

Many of the Xilinx pcores, e.g. ll_temac use a TCL script to check if a coregen generated netlist already exists and to generate one it if it doesn't exist.

/Mikhail

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Guru 19 years ago

Yes, Mikhail I know that. In fact I sucesfully implemented tcl script to generate fifo on the fly. But to properly create argument file (.arg) file for the purpose is a real "black magic" without a user manual (if it only exsisted). Right now I am on that mission to crate an arg file for fifo with asymetric ports. It is much easier to create a netlist and include it in /netlist directory.

Damn Xilinx, how can they make life miserable.

Cheers,

Guru

MM wrote:

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