Gaisler on a Spartan 3E Starter Kit?

Follow> The board uses a XC3S500 FPGA which about 10,000 cells.

So I may have to stick with OpenCores and/or whatever useful components I can extract from the Gaisler cores.

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David M. Palmer  dmpalmer@email.com (formerly @clark.net, @ematic.com)

David M. Palmer schrieb:

Hi David,

1) I have had LEON3 working in S3-400 fairly minimal system, so you should be able to get something working as well. 2) dont even dream of having Or1K uclinux ready system to fit s3e-500 3) you can experiment with MicroBlaze uclinux on s3e starterkit board see link below it has full details and refernece designs and uclinux images for the microblaze-uclinux for the s3e startkit

the hardware rev03 file seems to be broken though the download stops at

200kb before file end :(

Antti

I'm working on this. RS232 sender/receiver and DS2432 one-wire ROM id reader is finished:

The next big thing will be ethernet and DDR SDRAM support.

I'm very new to FPGA and VHDL programming, so any comments would be appreciated, especially if the Wishbone interface is implemented correctly, because I plan to use this interface for my other components, too.

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Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Thank you. The code works, but is it Wishbone? (This is not a rhetorical question, I don't know which of the signals are required and which optional.)

The Wishbone appnote

says the following are the signals. I have marked them with Y or N depending on whether your entity rs232_sender (for definiteness) has them:

1) Common signals: Y CLK_I Y RST_I N TAG_I/O 2) Data signals Y DAT_I/O 3) Bus Cycle signals Y ACK_I/O N ADR_I/O N CYC_I/O N ERR_I/O N SEL_I/O N RTY_I/O Y STB_I/O N WE_I/O

In contrast, the 10/100 Ethernet from OpenCores has all the signals except TAG and RTY. I don't know if that is because they are required in order to be Wishbone, or merely required for that particular core.

There are many other questions that I could figure out if I had an example of a complete system. For example, if you have many different registers in a core that you are addressing with the ADR lines, are you supposed ot decode all 32 address lines, or should there be a bus controller that recognizes the high-order address bits and controls STB and WE accordingly? Is that generated by Wishbone Builder?

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David M. Palmer  dmpalmer@email.com (formerly @clark.net, @ematic.com)

I don't think that you need all signals, e.g. the example on page 108 in the specification at

uses only ACK_O, CLK_I, DAT_I, DAT_O, RST_I, STB_I and WE_I. Ok, after reading it again, the required signals are:

For MASTER: ACK_I, CLK_I, CYC_O, RST_I, and STB_O For SLAVE: ACK_O, CLK_I, CYC_I, STB_I, and RST_I For SYSCON I'm not sure, but looks like CLK_O and reset RST_O.

So I have to add the CYC signals to my cores.

I don't know if it is required, but a bus controller would be a good idea anyway, because otherwise the address decoding logic has to be duplicated in every device and it makes it more difficult to change the address mapping, e.g. if you use a "generic" parameter in VHDL for specifying a 2 bit number for the highest order bits for selecting the device and the you need 5 devices, you have to change your core instead of just the memory controller.

No, I didn't know that such a tool exists and it was good for learning to do it manually, but for the next version I'll try the builder :-)

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Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Thanks to Frank Buss, I took another run at Wishbone, and it seems understandable now.

What are people's favorite Wishbone processors on Opencores? Something lightweight (say 16 bits and filling no more than a quarter of the FPGA), but preferably with gcc support.

I have pragmatic reasons for preferring free-as-in-speech and free-as-in-beer code for now.

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David M. Palmer  dmpalmer@email.com (formerly @clark.net, @ematic.com)