| The WISHBONE DATASHEET MUST indicate the port size. The port size | MUST be indicated as: 8-bit, 16-bit, 32-bit or 64-bit.
Does this mean I can't use dat_i for the update data? With Verilog and VHDL it is no problem to use 4 bit port sizes or even odd sizes, like 3 bits. Is there any other drawback if I use 4 bit dat_i, besides from not conforming to the Wishbone spec?
No, it just means that dat_i must be 8 bits wide (in your case) on the entity. It doesn't say that you have to use all 8 bits inside the architecture. When you go to synthesize this to a part, the synthesis will spot that those other 4 bits are not being used and optomize them away.
In order to document your component you would also have to document the actual data format anyway so for those unused four bits you could simply say dat_i(7:4) are 'Reserved for future use'.
KJ
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