ISE Webpack 8.1 adder wierdness

Have you tried with

assign result = (~b) + a + c;

Sylvain

I strongly guess that the flipflop has normal and inverted output. Therefore you get the inversion for free (for the cost of these flipflops). And furthermore it seems to be, that the pure combinational solutions are slightly to complex to fit into 8 LUTs (the inversion is too much to fit).

Ralf

Oooh, good idea. Trying it now... Whoa! this one used 22! For reference, here is the 22-LUT version:

module adder_test_22_luts(a, b, c, result); input[7:0] a, b; input c; output[8:0] result;

assign result = (~b) + a + c; endmodule

Todd

I don't see any reference to an inverted output on the flipflops in the Spartan 3 data sheet. From looking at the slice diagram in the DS and the schematic for ADSU8 in the library guide, it looks like the LUTs should be able to absorb the inverter on b.

Todd

Todd Fleming schrieb:

any signal inversion at LUT inputs are of couse "absorbed" so it should no make any difference if signals are inverted or not.

Antti

Well not always. In this case, yes it should because only 'b' is inverted. But if 'a' and 'b' were to be inverted, that couldn't be pushed into the LUTs because one of the two input has to feed the carry chain. The only modification that could be done on 'a' is AND it (with the MULAND (not sure of the name)).

The slice stucture allow pretty tricky/complex stuff to be done in just

Sylvain

I kept trying various approaches but was unable to find a way to get XST to synthesize an efficient structure, so I resorted to a structural description with XORXY and MUXCY using Verilog's generate.

Todd