Hi,
I have some problems with async clocked FIFOs in Altera Cyclone-II.
When simulating the design I receive data out from the FIFO after one clock pulse, but the timings diagram from the FIFO code generator indicates that I need to wait 3 clock cycles AND have the READ active during these 3 clock cycles!
From what I understand the simulation model coudl be wrong or the timings diagram is wrong.
What is correct in this, anyone been using these FIFOs and knows something about this?
/michael