Field-Programmable Gate Arrays

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Raggedstone1 PCI Shipping Build

Finally at last for all Raggedstone1 owners that have been asking there is now a new PCI shipping build available on ou...
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

sinmple DMA Example for ML403

Hello all, Does anybody have a simple dma example that dma's from a custom peripheral to the SRAM or SDRAM on the ML403...
3 comments posted 20yrs
posted by hstello
3 comments posted 20yrs posted by hstello

FIFO with EBR

Hi, I have tried to synthesize the synchronous fifo example "FIFO.vhd" from Ben Cohen's book "Real Chip Design and Veri...
8 comments posted 20yrs
posted by ALuPin
8 comments posted 20yrs posted by ALuPin

Clock Domain Crossing in Virtex4

Hello, i'm designing a onchip bus on a Virtex4 FPGA with one master and several slave modules located in different asyn...
1 comments posted 20yrs
posted by talt
1 comments posted 20yrs posted by talt

MIG1.6 as DDR2 controller using Spartan3

Hi, I wonder if anybody has a positive experience with Xilinx MIG1.6 (or earlier version) as a controller for DDR2 memo...
1 comments posted 20yrs
posted by szumu
1 comments posted 20yrs posted by szumu

Virtex2Pro: Xilinx PCI core mapping error

Synthesise PCI ver.3.160 for XC2VP7-6FG458 in Coregen (ISE 8.2 SP 2). When run compile, ISE genegate ERROR: Using targe...
7 comments posted 20yrs
posted by axalay
7 comments posted 20yrs posted by axalay

How to resolve a Xilinx 8.1 BlockRAM problem

Hi, I need your help. My project uses BlockRAM by Xilinx. I used CoreGenerator 6.2 to generate BlockRAM bram64_8, and X...
4 comments posted 20yrs
posted by wtxwtx
4 comments posted 20yrs posted by wtxwtx

wiring resource utilization?

Hi Given a design placeed and routed in FPGA, I need to know "how much wiring resources my implementation are using out...
3 comments posted 20yrs
posted by pasacco
3 comments posted 20yrs posted by pasacco

Xilinx VSK (Video Starter Kit)

I would like to exchange information on the Xilinx VSK with others using the kit. In particular I have the following ob...
2 comments posted 20yrs
posted by dakkumar
2 comments posted 20yrs posted by dakkumar

Spartan-3 Starter Kit newbie question

I bought a Spartan-3 kit about a year ago and it came with V7.1i of the software, I'm wondering what the kits are shipp...
2 comments posted 20yrs
posted by cbayona
2 comments posted 20yrs posted by cbayona

FIR Implementation with System Generator 8.2

I am a newer of System Generator. I designed an FIR with system generator, only using the Delay, Cmult, Addsub, upsampl...
3 comments posted 20yrs
posted by lqo2
3 comments posted 20yrs posted by lqo2

gpio help...

I've got a ML403 Virtex 4 development board with an FX12 part on it. I've developed several VHDL components that I need...
6 comments posted 20yrs
posted by starfire151 AT cableone DOT net
6 comments posted 20yrs posted by starfire151 AT cableone DOT net

xilinx bootloader help...

I'm using an ML403 development board. The board has a Compact Flash card on it, as well as SRAM, DDR RAM, Flash, etc. I...
0 comments posted 20yrs
posted by starfire151 AT cableone DOT net
0 comments posted 20yrs posted by starfire151 AT cableone DOT net

Forth-CPU design

After thinking about how a "normal" CPU could look like, I've tried to design a Forth-like CPU: http://www.frank-buss.d...
41 comments posted 20yrs
posted by fb
41 comments posted 20yrs posted by fb