Field-Programmable Gate Arrays

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linux 2.4 v 2.6 on xilinx

I have a xilinx soc that is running 2.4 of the PPC linux fine. To run 2.6 is it just a matter of copying the arch direc...
8 comments posted 19yrs
posted by someone
8 comments posted 19yrs posted by someone

I do not know this !

I like to start FPGA but I have access to a CPLD traning kit . I would like to know : 1-If I start with CPLD (XC9572 th...
3 comments posted 19yrs
posted by sadatakhavi.ali
3 comments posted 19yrs posted by sadatakhavi.ali

Qestion about the ability of synthesis

Hi, I am new to VHDL. I write the following simple counter program in ISE webpack 8.2. Both two can be behavior simulat...
14 comments posted 19yrs
posted by rxjwg98
14 comments posted 19yrs posted by rxjwg98

EDK 7.1

Hi, Iam using Xilinx EDK 7.1 and have integrated a 4-bit adder as a custom ip. For the adder ip i have made use of 4 so...
1 comments posted 19yrs
posted by acetracerbullet1000
1 comments posted 19yrs posted by acetracerbullet1000

Impossible to download WebPACK?

Is it actually possible to download WebPACK? I tried using my existing xilinx.com account to download it, and I get int...
28 comments posted 19yrs
posted by zwsdotcom
28 comments posted 19yrs posted by zwsdotcom

Read from Microblaze

Hi all, I want to do the read out from GPIO (like DIP SWITCHES or Buttons) in Microblaze using the xgpio_DiscreteRead p...
1 comments posted 19yrs
posted by jerzy.zielinski
1 comments posted 19yrs posted by jerzy.zielinski

5V FPGAs & CPLDs in 2006?

What would people's opinion on using a 5V FPGA (or possibly large-I/O-count CPLD) for a new, but limited run in-house-p...
3 comments posted 19yrs
posted by cs_posting
3 comments posted 19yrs posted by cs_posting

Higher voltages input, quick check....

I need to interface some 12 and 24V signals to an FPGA/CPLD, it'll probably be one of the low end Spartans or Cyclones....
18 comments posted 19yrs
posted by nial
18 comments posted 19yrs posted by nial

logic partioning -- why not after mapping

Why is logic partioning considered better on pre mapped design only and not on post mapped netlists ..... one reason i...
1 comments posted 19yrs
posted by groups.tech
1 comments posted 19yrs posted by groups.tech

V4 PPC-linux dlclose() SIGSEGV

Hi while waiting for the www.lynuxworks.com V4Fx linux 2.6.x release I wonder if there is a quick fix to get shared lib...
0 comments posted 19yrs
posted by Antti.Lukats
0 comments posted 19yrs posted by Antti.Lukats

Sluggish FPGA Editor/floorplanner/etc in Linux

I have long been irritated that some of the tools in ISE are quite sluggish in Linux. For example, suppose I run a synt...
0 comments posted 19yrs
posted by ehliar
0 comments posted 19yrs posted by ehliar

Synthesize IEEE fixpoint Library with Xilinx ISE 8.2i

Hi everyone, has anybody successfully synthesized the IEEE 1076-2006 libary, which includes a fixed-point implementatio...
0 comments posted 19yrs
posted by peter.kampmann
0 comments posted 19yrs posted by peter.kampmann

problem generate PCI-32/66MHz with Coregen

Coregen report me: DEBUG[cmsg] - EJava Unzip Failure on v3.0.160.zip for D:\Xilinx\testCOREGEN\tmp\_cg\_bbxjava.util.zi...
3 comments posted 19yrs
posted by axalay
3 comments posted 19yrs posted by axalay

MicroBlaze and RAM Application

Hi all. I'm more or less a beginner in using Xilinx tools and System. Now I'm working with a Spartan 3E Evaluation Boar...
1 comments posted 19yrs
posted by alfredo.aletto
1 comments posted 19yrs posted by alfredo.aletto