Hello,
i'm designing a onchip bus on a Virtex4 FPGA with one master and several slave modules located in different asynchronous clock domains. The bus consists of address, data and control signals. For synchronization i'm using a full hanshake with a "Request" and "Acknowledge" signals. Now it would be interessting to know if it's enough to synchronize only the handshake signals as long as i make sure that the other bus signals are stable for a certain amount of time or if i have to synchronize the address and control signals as well. To illustrate the problem lets assume the following situation:
There are 2 signals coming from the source clock domain CLK_S called "SIG_A" and "REQUEST" and entering the destination clock domain CLK_D. SIG_A is set a few clock cycles before REQUEST and then capt stable. REQUEST is synchronized in the destination clock domain CLK_D with two flip-flops. The synchronized signal is called REQUEST_SYNC. This signal is used to decide if the signal SIG_A is stored in the clock domain CLK_D. So the code would look like this
REG : process(CLK_D) begin if rising_edge(CLK_D) then if REQUEST_SYNC='1' then Q