wiring resource utilization?


Given a design placeed and routed in FPGA, I need to know "how much wiring resources my implementation are using out of total wiring resources".

I am using Xilinx Virtex-II Pro. In PAR report, logic (slice, LUT, FF,...) resource utilization (in percentage) is available. But, wiring (wire, switch box) resource utilization (in percentage) is not available.

Question is that

  1. How can we know wiring resource utilization?
  2. Can "number of used switch box" out of "total number of switch box" be a metric of wiring resource utilization? If yes, are there any method to know that?

Thankyou for remark, suggestion.

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Why do you need to know the wiring resource utilization? The current crop of devices have ample wiring resources, and as long as it routes and meets timing, why does it matter how much is used? Designs use a very small percentage of the available routing resources. However, the high density of wiring is present in order to increase the likelihood of a route solution that meets timing. The actual routing resources used wil depend heavily on the place and route solution, which can change considerably with very small changes in the design. Because of these facts, the routing resource utilization has little value to the user of the devices.

Reply to
Ray Andraka

If you are really worried about it ... take a look using the FPGA editor in the areas you have some concerns.

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This is generally true... as long as device utilisation is well under

100%. I had a job with a small research group some years ago where we had one person working full-time on analyzing timing reports and write routing constraints. IIRC, the devices in questions were Virtex 4000 (two per board) and our FAE said we would never be able to route and even less meet timings beyond about 85% logic utilisation... but in the end, we managed to get nearly 95% with over 2k hand-written routing/placement constraints and 10+ hours synthesis run-time a pop.

Many of the older FPGAs are not 100% routable even for nearly trivial logic. Newer devices are said to be "100% routable" but once timing is taken into account there probably is no device that can achieve 100% non-trivial logic utilisation. Given how synthesis times explode once device utilisation exceeds 70%, exceeding 90% today is still generally not recommended.

As you said though, knowing how much of the routing fabric is used is of little use. What IS really important is knowing HOW it is (mis-)used - that's what the full-time constraints guy was doing.

I suppose routing utilisation could still be interesting to have in the "stats that are nice to know about but have little to no relevance" category.

Daniel Sauvageau
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Daniel S.

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