Mostly for xilinx people,
xapp802 Xilinx XAPP802 Virtex Series Memory Interface Application Notes Available here:
On page 3 is figure 2. There is an FDDR shown on the diagram that has left and right data going into the D0 and D1 inputs, but both clocks are coming from the same source (CLK0 from the DCM). Shouldn't C1 be coming from the CLK180?
-Dave