Mostly for xilinx people,
xapp802 Xilinx XAPP802 Virtex Series Memory Interface Application Notes Available here:
On page 3 is figure 2. There is an FDDR shown on the diagram that has left and right data going into the D0 and D1 inputs, but both clocks are coming from the same source (CLK0 from the DCM). Shouldn't C1 be coming from the CLK180?
-Dave
Notice the clock inversion circle on one of the clock input pins.
(I hope Xilinx explain their schematic conventions somewhere - not everyone still has those fat orange (sorry Peter - red) books on their shelves!)
- Brian
The inversion bubble is an IEEE standard.
After I posted I did notice that but I wanted confirmation. I think of a solid round dot as a connection. An inversion bubble is usually a circle. Also their dot seems embedded in the device, it should stand out more.
-Dave
Have something to add? Share your thoughts — no account required.
Ask the community — no account required