Lattice ECP2/M

John_H schrieb:

WAU - the XP2 will also have SERDES (but comes maybe later this year), but having the super ECP2 lowcost family extended with 3GBs SERDES was defenetly a good move !!

Antti

The pricing I have gotten on the ECP2 line is attractive, but in the grand scheme of things I don't see where it is a significant difference with the other players in the field. I think that optimizing any given parameter in the FPGA market is a matter of timing. A couple of years ago Spartan 3s were the low cost chips, then when the Cyclone II parts came out they were a bit cheaper. Now that ECP2 parts are starting to show, they will be cheaper... until the Spartan 4/5 parts make it to the scene.

If only there was something that actually distinguished the different families of parts!

Rick,

Have you ever seen a high speed serdes and plenty of mem blocks on any of the low cost families of either Xilinx, Altera?

I definitely believe that these features are distinguishing this family from the other players!

Of course, I haven't seen anything from Xilinx or Altera yet that would prove the opposite, maybe you have... but don't want/can't share with us due to NDA's

Regards,

Luc

The ECP2 line is nice but not terribly remarkable.

The ECP2M parts, on the other hand, blow past the Brand A and Brand X low-cost offerings on memory to logic ratios *and* are the first low-cost devices to include SERDES functionality and at *very* attractive per-channel power levels.

My attention was attracted to the offering because of the memory. Adding PCI express would be quite a bonus for me.

Hello John, thanks for the kudos. If you'd like to give any feedback or comments on the new family, Bertrand Leigh, Lattice's director of apps engineering, has posted a blog about the new LatticeECP2M FPGA here:

rgds, Bart Borosky, Lattice

Please don't get me wrong, I am not knocking any of these parts. But I don't see a serdes and being a valuable addition to a low cost FPGA. Normally the items you are interfacing to with a serdes are not so cheap, but maybe I am not current and serdes are more popular now. But I see it as similar to the conversation where someone was complaining about needing to use $0.09 FETs for a high current interface rather than the low cost $0.03 cent 7002 FETs because the 3.3 volt interface on the FPGA would not drive the FET fully. Even a cheap FPGA is around $20 in most designs, so what is the diff on a few cents on the FETs? LIkewise, what is the diff on a $40 FPGA rather than a $20 FPGA if it interfaced to a $200+ fiber interface?

Personally what I want is a good $10 FPGA with 260 IOs. So far they are all about $20. If it has more memory to support an imbedded MCU, all the better!

Not all SERDES go into optics, and in fact many never leave the printed circuit board. Low-cost devices with SERDES can help with multi-device designs, where extra devices are more cost-effective than a single device with the required number of I/O's. Using high- speed SERDES from chip to chip reduces the interconnect pin count giving you more of the I/O you added the parts for. I would think the ASIC simulation guys would snap these parts up...

Definately a market shaker is my comment given the current interest in high speed links we are seeing.

John Adair Enterpo> rickman wrote:

per-channel