Are you ready for Virtex-5? We are...

OOPS, I forgot to point out that the part number must have ES at the end of its name, e.g. XC5VLX30-1FFG324CES.

ES stands for "Early Silicon". The absence of these two letters would declare it a "volume production" part (which is not available yet), and the order would automatically be rejected. One can never be too precise, especially with computerized order entry. Peter Alfke

Peter Alfke wrote:

Why can't we get the errata as simple as the datasheet ?. Seems crucial for ES devices.

Karl.

Karl,

How easy is that?

Austin

Not easy enough. I have to register.

Karl.

I thought "ES" stood for "Engineering Sample"....learn something new every day...

Alan

Karl,

Does that mean you will not use Virtex 5?

Austin

It might sound silly, but sometimes that is all it takes.. (Especially if the process is not fully automated, but I don't know whether that is the case here).

Cheers, Jon

We are only interested in serious designers, not just "tire-kickers". The registration is not a hurdle if you are serious.

BTW: In this case, the errata are really trivial: a register that must be reset a special way, a reduced max frequency in synchronous FIFO mode, a missing optional clock inversion somewhere...

"Early Silicon" is my interpretation of ES. To call it "Engineering Samples" would be misleading. These are full-quality, fully tested and characterized parts that work over temperature and voltage ranges.

This is Early Silicon, and any design error (and there often is, since nobody is perfect the first time around) it is described on an errata sheet. By definition, every ES device has an errata sheet; at best the sheet just says: No errata! The errata will be fixed in the production (non-ES) version. That's why we suggest that you avoid, if you can, shipping our ES parts in your production equipment. Saves you some logistic confusion.

We are excited that the Virtex-5 parts came out so clean, and with good manufactur> Aust> > Karl,

How about some budgetary prices for low volumes? I'm Dutch so my first question is always: "How much does it cost?".

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Utter bullshit. Usually you write very fair replies but this is just nonsense. I have ES1 and ES4 parts from Xilinx that are only sold as no refunds, no returns, with major components that do not work. They are not full quality at all. These particular Virtex 5 parts may be very good, but it is certainly not true for your entire product range and people should not be mislead in to believing otherwise.

Thus not "full-quality"

What can I say, I made the mistake of not delaying design-in of Virtex

4 FX parts and am still paying the price today.

Cheers, Jon

I wanted to stress that ES parts are tested and reliable. They do not wear out or slowly go bad on you. The Virtex-4FXES devices had severe functional and parametric (but not "reliability") problems, as covered in the errata sheets. We are all very sorry about this, and we have made sure that the next generation design is far more robust. Peter Alfke

To be fair, I've have no problems with what is isn't listed in the errata.

Cheers, Jon

I think some slack needs to be cut for Xilinx here :-) At least they are clearly labelling their ES parts (be engineering sample or early silicon) as such. If any of you use an Intel or AMD cpu ;-) go to their respective web sites and look for the errata on the shipping products. Intel's latest cpu has tens of erratas some of which will be fixed in a later stepping. AMD's cpu have around half a dozen which won't be fixed. Anyone who has done any IC development knows how difficult it is to get it right but most of us do, ... eventually.

Hi Austin,

If I was an engineer and would like to know about the how and what, an registration requirement, would make me think twice, yes.

Kind regards, Karl.

Peter Alfke schrieb:

[...]

It doesnt help much if Xilinx is ready for Virtex-5 it matter if the customers are.

I have Virtex-5 on the desk already for over weeks, yes shipped by Avnet as normal order and I am looking to buy ML501 board NOW but

1) ML501 doesnt seem to be available from Xilinx or Avnet? 2) Virtex-5 MicroBlaze was supposed to be supported in EDK 8.2 SP2 targetted mid Aug - now looking at Xilinx website the EDK SP2 release date is slipped to mid Oct.

mid Oct it may again be slipped to Mid Aug?

The reference designs for ML501 are downloadable, but ASFAIK they requires EDK 8.2 SP2 what is not available, so even it may be possible to obtain V5 silicon NOW there support for Virtex-5 just isnt there for the Xilinx customers. And for us who are not Xilinx employees it really doesnt matter how long Xilinx personell has had fun with latest silicon

- until both the silicon AND tools are available there is no supprort. So no matter how ready we may be for Virtex-5, and belive me some of us really are - we are not really able todo any real work until tools support is also made available by Xilinx.

Antti

FPGA programming without FPGA vendor tools!

Antti schrieb:

[my own ***** snipped]

EDK 8.1 SP1 has Virtex-5 MicroBlaze 5.00.a and 5.00.b in it it is just labelled as "early access" but its readily available. there is some minor mess with MPD files like FSL bus is not supported (eg requires manual edit of the MPD) but otherwise the Virtex-5 can be targetted ok on EDK 8.1 SP1, eg no need to wait for SP2

here is the picture of the EDK system with Virtex-5

Antti

Peter Alfke schrieb:

ll

Hi Peter,

the order code left my hands, but I am not sure when the order was (or will be) placed. Its beeing processed and I will monitor the process.

As of availability of Virtex-5 from distrubutors I can confirm that XC5VLX50--FF676 arrived from Avnet about 3 weeks ago already.

So they are orderable, and have been sent out and reached the customer(s).

Virtex-5 support in EDK 8.1 SP1 is defenetly there, and G=F6ran was even so kind and tested out a MicroFpga Virtex-5 bitstream on ML501 board.

It just worked as made - a fresh new Virtex-5 EDK system worked on real silicon with the first attempt. So it is possible to create Virtex-5 SoC systems with EDK 8.1 SP1 that just work.

Antti

Antti schrieb:

will

uups 8.1 above should be 8.2 of course, Antti