Field-Programmable Gate Arrays

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ISE On Intel Mac

Is anyone running ISE on an Intel based Macintosh? I'm considering a MacPro with dual Core 2 Duo processors, running ISE...
2 comments posted 20yrs
posted by user
2 comments posted 20yrs posted by user

WebPack on Linux

Greetings How is this supposed to work ? I have installed webpack for Linux on my FC5 box, and that part is working. I...
14 comments posted 20yrs
posted by henrik.kirneh
14 comments posted 20yrs posted by henrik.kirneh

lwip xilinx

hi i'm using a microblaze system with lwip raw api. i'm trying to get the sample code to work but it's not working. my...
0 comments posted 20yrs
posted by u_stadler
0 comments posted 20yrs posted by u_stadler

Synthesizing Xilinx Coregen cores

Hey every1, I just created a memory with Xilinx coregen and it uses the CAM_V4_0.v xilinx file. When i try synthesise e...
1 comments posted 20yrs
posted by robquigley
1 comments posted 20yrs posted by robquigley

Virtex-5 LXT launched today !

http://www.xilinx.com/prs_rls/2006/silicon_vir/0696v5lxt.htm already pricing given for 1000qty not bad at all. unfortun...
19 comments posted 20yrs
posted by Antti.Lukats
19 comments posted 20yrs posted by Antti.Lukats

buying xilinx spartan 3E kit just for EDK ?

i already have starter board for xilinix spartan 3, which i bought directly from digilent (so i did't receive EDK CD)....
3 comments posted 20yrs
posted by manusha
3 comments posted 20yrs posted by manusha

User peripherals within a Nios system

Is it possible to have a connection between two seperate user peripherals inside a Nios 2 system? Or do I have to route...
2 comments posted 20yrs
posted by someone
2 comments posted 20yrs posted by someone

WiFi signal repeater using any virtix fpga

I just started learning about fpga technology, I am looking for a solution to this minor problem. I'm supposed to build...
2 comments posted 20yrs
posted by ramukumban
2 comments posted 20yrs posted by ramukumban

Low hierarchy not follow in ChipScope Pro

Hi all, I have ChipScope Pro 7.1. I successfully evlauate all signal of top module my design. Now i want to also evalua...
2 comments posted 20yrs
posted by naumanqau
2 comments posted 20yrs posted by naumanqau

Synopsys's VMM and Mentor's AVM

Hi all, I want to use SystemVerilog to construct next generation of my testbench. And I found Synopsys provide VMM whil...
11 comments posted 20yrs
posted by zhushenli
11 comments posted 20yrs posted by zhushenli

boundary scan, JTAG

I found: http://www.xilinx.com/xlnx/xil_tt_gettingstarted.jsp?sProduct=JTAG&iLanguageID=1&iCountryID=1 which states: "B...
0 comments posted 20yrs
posted by austin
0 comments posted 20yrs posted by austin

uClinux for MicroBlaze ver 5.0

Hi it seems that full MicroBlaze ver 5 uClinux support is now there - required is GCC toolchain based on EDK 8.2 (to ha...
0 comments posted 20yrs
posted by Antti.Lukats
0 comments posted 20yrs posted by Antti.Lukats

echo $LM_LICENCE_FILE not working

hi got the tester of model sim from altera, but it seem even though i set the environment var from the system control p...
9 comments posted 20yrs
posted by jackokring
9 comments posted 20yrs posted by jackokring

Nand Flash programming times

Is it possible to grab video or still frames directly into a NAND flash? Is it a common practise or are such devices sti...
2 comments posted 20yrs
posted by me
2 comments posted 20yrs posted by me