boundary scan, JTAG

I found:

which states:

"Boundary Scan tests on Xilinx devices should only be performed after configuration under the following circumstances:

-When configuration cannot be prevented

-When differential signaling standards are used"

So, before configuration, the IO pin will be the default IO standard (LVCMOS12_F), and after configuration, the IO standard will be that as programmed by the configuration.

Austin