Synopsys's VMM and Mentor's AVM

Hi all,

I want to use SystemVerilog to construct next generation of my testbench.

And I found Synopsys provide VMM while Mentor provide AVM. Anyone can give some comment on these two methodology? Or are they similar?

I don't know if Synopsys's VMM is open document and open source code.

The AVM cookbook/source code, you can download a free copy from:

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Best regards, Davy

Reply to
Davy
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Davy, sorry for the non-answer, but you may get better results with that question at

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/Ed

Reply to
EdA

A comparison of AVM and VMM in Verification Horizons:

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PDF version:
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Four articles in the EETIMES on the SystemVerilog reference verification methodology:

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The first is by Mentor, the second by Synopsys (IIRC). Both of course with their own biases.

As far as I know the VMM book is not an open document:

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The AVM cookbook clearly is.

The same goes for VMM and AVM itself. AVM is opensource, VMM source is heavily licensed (word choice from Verification Horizons).

--
Paul.
Reply to
Paul Uiterlinden

Hi Paul,

Thanks a lot! I also want to know does Cadence provide such verification methodology like Synopsys and Mentor.

And what's Synopsys (IIRC)'s IIRC mean?

Best regards, Davy

Paul Uiterl>

Reply to
Davy

Hi,

Paul Uiterl>

I don't understand this - perhaps you are mixing "open" with "free"? VMM is a published book so why is it not open? Infact we wrote a book on "pragmatic approach to VMM adoption" based on that book. (See

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if interested). BTW, VMM also ships under $VCS_HOME/doc.

Quoting from:

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SNPS gives source code to VCS users if they request for the same.

Now having said all this, given the status of SV implementation by major eda vendors, neither VMM nor AVM is truly "portable" as of today

- tools support different subsets just to fit into their individual methodology, perhaps the tool development was driven by the methodology team. So when 100% SV implementation is available across vendors, users may not have an issue of AVM vs. VMM as both will work in any simulator.

Now, I'm teaching myself AVM and am finding it quite similar to VMM. Sure VMM has much more stuff, also maturity (given their RVM legacy), AVM has some "new" concepts such as analysis ports etc. I asked Mentor if I can openly debate on AVM, no reply yet...

Regards Ajeetha, CVC

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Reply to
Ajeetha

Not that I know of. I haven't come across it, but I haven't actively been searching for it.

IIRC is just an abbreviation for "If I remember correctly". Sorry for the confusion.

--
Paul.
Reply to
Paul Uiterlinden

Yes, I am. What I meant it is not freely down-loadable.

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"VCS customers may license the source code at no additional cost to gain insight into the implementation details."

So that's for VCS users. I'm not a VCS user, so I do not have access to the source code. In that way it _is_ licensed. The AVM source is not.

I cannot comment on this. I haven't used or really studied neither of them. I did find this quote from Verification Horizons quite potent:

"(...) I mention this story because it is similar to the thought process that many of you may be going through in trying to decide how to adopt a new verification methodology. You have a similar choice to make - should you go with the AVM or take a look at the VMM? In my minivan story, the VMM is the used car since it?s really based on old technology, having simply been ported from OpenVera® to SystemVerilog. The AVM is the new topof-the-line car that gives you all of the latest features and the power and flexibility that you need. Plus your tool and legacy investments are protected because it is based on an open standard. Which would you rather use to carry your precious cargo?"

Granted, this is by Mentor Graphics, so perhaps should be taken with a grain of salt. I really do not have the knowledge to put a value on quotes likes this. Perhaps you would like to comment on this.

Call me naive, but I do not see why such a debate should not be possible. It's a free world, "free" as in "free speech", not as in "free bear".

--
Paul.
www.aimcom.nl
Reply to
Paul Uiterlinden

[snip]

Hi Ajeetha,

Thanks for the explanation. I think a lot of people will be interested in your openly comment on both VMM and AVM without biased opinion. For AVM, it use Apache licence. Is this licence forbid openly debate :)

Best regards, Davy

Reply to
Davy

Hi Davy, > Hi Ajeetha,

That's one of the reasons for me to hold back :-) As I have to be

100% correct else Mentor and/or SNPS folks will start pin pointing errors with my analysis. I would take some more time, but from quick analysis so far, both are very similar in concepts and I am even considering an "adaptor" for AVM users to VMM and vice versa - but all in thoughts, depends on market.

Honestly speaking I have NOT read through the license in full and am not a lawyer either. Hence I would be glad if someone clearly says "yes we can debate on it". Being an independent consutlant I want to be friendly to all vendors.

Regards Ajeetha, CVC

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Reply to
Ajeetha

[snip] Hi Ajeetha,

I agree with you. And I have sent a mail to apache.org (Apache License V2 owner) to ask the problem. I will give out the result when got a replay.

Best regards, Davy

Reply to
Davy

Mentor Graphics encourages open discussion of anything we have published at

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This is why we published it in that form.

Any code or pseudo code that uses the AVM is fine. Questions refering to specific items in the documentation are fine.

If you're going to post the contents of the library itself you already have permission under the license to do so provided you also copy the header at the top of the file which includes the copyright notice - although I would have thought this would be unecessary most of the time.

Adam.

Adam Rose Verification Technologist Mentor Graphics.

Reply to
Adam_Rose

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(check the last two posts), Cadence seems to have a verification methodology called UVM..

Reply to
googler

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