Hi all, I have ChipScope Pro 7.1. I successfully evlauate all signal of top module my design. Now i want to also evaluate all signals which is instantiate in top module. For this i just add ChipScope on that particular file and add ILA core and finally select signals. But finally when i implement design, synthsiser skip the inserted ILA core. Can any body tell me how i can monitor low lvel signals without porting these in TOP file.
_____ UART TOP______ --------> Successfully Done thr ILA | | UART RX UART TX ---------> How i monitor | | RX_SM TX_SM --------> How i monitor
Best Regards