Hey every1,
I just created a memory with Xilinx coregen and it uses the CAM_V4_0.v xilinx file.
When i try synthesise everything with Leonardo Spectrum it errors out:
"C:/Xilinx/verilog/src/XilinxCoreLib/CAM_V4_0.v", line 671: Warning, system task enable ignored for synthesis "C:/Xilinx/verilog/src/XilinxCoreLib/CAM_V4_0.v", line 700: Warning, initial statement not supported. Ignored "C:/Xilinx/verilog/src/XilinxCoreLib/CAM_V4_0.v", line 769: Error, Before all asynchronous conditions have been tested, checking for other expressions is not allowed
When i looked into CAM_V4_0).v it looks like a behavioural model and has lots of things that wont synthesise. Does the coregen have any options for synthesisable output? Or any1 got any ideas - am i going about this the wrong way?
This is my first attempt at using the coregen tool.
Cheers for any feedback,
Rob.