Field-Programmable Gate Arrays

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Systolic Viterbi Decoder ?

Hi, Sorry for the cross-post, but I think this is a relevant topic in both newsgroups. Has anyone come across this pape...
0 comments posted 19yrs
posted by callmevc
0 comments posted 19yrs posted by callmevc

Libero 7.2

Hi to everyone, i've started using Libero 7.2 and I found a very nice feature (let's say), when you import package file...
6 comments posted 19yrs
posted by alessandro.basili
6 comments posted 19yrs posted by alessandro.basili

how to change cclk frequency ?

how to change the CCLK frequency for FPGA in master-serial mode? I try to set the clock rate to higher rate in ISE when...
5 comments posted 19yrs
posted by wolflame
5 comments posted 19yrs posted by wolflame

Looking for internship near Toronto

I am currently in my 3rd year of Electrical Engineering undergrad at Ryerson University in Toronto, Ontario, Canada. Th...
1 comments posted 19yrs
posted by x86asm
1 comments posted 19yrs posted by x86asm

Question about lib manual of Xilinx

Hi, The following is the VHDL example on page 699, Libraries Guide, ISE 8.1i. I have two questions in this example. 1....
0 comments posted 19yrs
posted by rxjwg98
0 comments posted 19yrs posted by rxjwg98

EDIF Design Entry tools

HI all how can one use an edif netlist of a design to add components to it either in schematic or vhdl and verilog? is...
8 comments posted 19yrs
posted by avionion
8 comments posted 19yrs posted by avionion

FPGA comparision

Hi, i would like to know which is the best if i want a FPGA ( with 150k virtex4 equavalent LUTs) and low cost. thanks in...
7 comments posted 19yrs
posted by subin.82
7 comments posted 19yrs posted by subin.82

Scoreboard and Checker in Testbench?

Hi all, IMHO, there is something compare the golden output and DUT output in testbench (I call it Checker). But in veri...
15 comments posted 19yrs
posted by zhushenli
15 comments posted 19yrs posted by zhushenli

Xilinx V4 not registering T at OLOGIC

The following code: output_process:process(clk) begin if( clk'event and clk='1') then mem_a
4 comments posted 19yrs
posted by bradsmallridge
4 comments posted 19yrs posted by bradsmallridge

DDR Address

Hi, Is it ok not to connect at least one DDR Address signal to a ddr controller? If so, should i connect it to GND or VC...
5 comments posted 19yrs
posted by yy7d6
5 comments posted 19yrs posted by yy7d6

more than 90% occupancy in an Actel FPGA

Hi to everyone, I'm using an Actel fuse A54SX72A, which has 2012 sequential cells and at the moment I filled it up to m...
6 comments posted 19yrs
posted by alessandro.basili
6 comments posted 19yrs posted by alessandro.basili

DDR SDRAM static timing analysis

Hi, I need a help in static timing analysis for DDR interface to network processor . Processor say that its timing is a...
1 comments posted 19yrs
posted by pinku1979
1 comments posted 19yrs posted by pinku1979

Xilinx FPGAs in battery-powered scenarios

Hey, I've been reluctant recently on envisaging a Virtex-4 device as being operational in a battery-powered situation....
32 comments posted 19yrs
posted by mloulah
32 comments posted 19yrs posted by mloulah

Virtex-5 LXT orderable?

http://www.sierraic.com/pnresults.asp?part=XC5VLX50T1FF1136CES there is status "available" - and full order code as wel...
5 comments posted 19yrs
posted by Antti.Lukats
5 comments posted 19yrs posted by Antti.Lukats