I am finally at the synthesis portion of the course. My code "compiles", simulates, sythesisizes and implements correctly (with green check mark). But I am to get some info from the XST reports that I may not understand fully.
I'm fairly certian I've collected all the data the professor requires aside from the list below.
- "netlist shematic" (where do I find/how do I generate this?)
- "waveforms from timing simulation" (are these sythesis specific, or are these just my modelsim simulation waveforms?)
and he also asks for the min/max clock freq, with slack times after a) sythesis, b) mapping and c) p&r
I will have to define a clock period I assume? Do I enter this via the constraint editor? If so, maybe a syntax example of how I might do this? After that I just need to view the timing reports after each process (a,b and, c)?
I hope these questions are fair. I've read through some provided Xilinx literature, but I'm still a little lost...obviously.