Getting info from XST, Homework Question, netlist, reports, etc...

I am finally at the synthesis portion of the course. My code "compiles", simulates, sythesisizes and implements correctly (with green check mark). But I am to get some info from the XST reports that I may not understand fully.

I'm fairly certian I've collected all the data the professor requires aside from the list below.

- "netlist shematic" (where do I find/how do I generate this?)

- "waveforms from timing simulation" (are these sythesis specific, or are these just my modelsim simulation waveforms?)

and he also asks for the min/max clock freq, with slack times after a) sythesis, b) mapping and c) p&r

I will have to define a clock period I assume? Do I enter this via the constraint editor? If so, maybe a syntax example of how I might do this? After that I just need to view the timing reports after each process (a,b and, c)?

I hope these questions are fair. I've read through some provided Xilinx literature, but I'm still a little lost...obviously.

Thanks, Kyle

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Kyle H.
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still lost on this part, even more lost after talking with someone about it.

same, I must be missing something very important here, from my understanding they are not modelsim simulation waveforms, but still don't know where to start.

I've defined a timing constraint and I am able to come up with min/max/slack, but I don't understand how to get it after each of the three steps above (still).

Reply to
Kyle H.

Perhaps you want the "RTL schematic"?

I would assume these are the waveforms from Modelsim, however you need to simulate the back-annotated design, not the behavioral simulation. This is very straightforward if you use the Project Navigator GUI in ISE. If your testbench is included in the project you can list the processes available for the testbench and start Modelsim from the GUI with the appropriate model:

Behavioral Post-Translate Post-Map Post-Place & Route

Again with the Project Navigator GUI you have items in the process window for "static timing" after each stage of the design (the post synthesis timing is part of the synthesis report). You may need to open up the process hierarchy a bit (click on the "+" signs) to find these: Post-Map Static Timing Report Post-Place & Route Static Timing Report

Good Luck, Gabor

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