playing with ML501, first impressions

Virtex-5 Evaluation board ML501 Testing ============================= Preloaded designs: All CompactFlash demos worked (did not check the WebServer as the IP address doesnt much my settings) Demos from Platform flash started Demos from Paralle flash also (can choose one of 4 configurations) SPI Flash seems to be empty, eg no design starts (or I didnt find the mode selection?)

MicroFpga LED show demo also worked GPIO LEDs at the left front corner did blink.

After updating ChipScope the V5 sysmon did become visible in ChipScope analyzer.

Testing PLL's and configuration clock - connected 50MHz config clock to PLL, setting multiply to 7, then FX output to spare pin extension header and voila 300+ MHz frequency measured.

u-Boot ======

After adding ML501 support for u-boot 1.1.4 verified that the images worked with XSIM platform simulator. Then tried on ML501 and here it did not work, created ACE file, copied to cfg6 position ("my ace") selected cfg from boot menu, and nothing only ERR2 (OPB error) goes red. Ok that was my fault, I had compiled the u-boot with barrel shift enabled and ML501 reference design had no barrel shift enabled, and unfortunatly XSIM 1.3 doesnt have option to disable barrel-shift so the problem was found with simulator. After u-boot was recompile with proper settings, well it still didnt start from system ACE, but started ok when loaded from XMD. When generating the ACE file, well it did took really long, and the files generated did appear to be too big over 3MB (4MB for the u-boot), even after compression with Xilant's ace compressed the ACE file size was still way over 2.5MB, the ACE files on the CF card are however all about 1.6MB. So I had to force use fsl option in genace.tcl, now the uboot.ace was also correct size and ACE file generation was quick again.

Tried to download the ACE file over JTAG using ACE Player, failed, ah sure the chain is not setup properly as it looks different from the external connector to what the system ACE sees it.

Tried to generate some ACE file from the XPS GUI, first attempt created file for v4FX12 ! This was due wrong version of genace.tcl being found on the path, moved the genace.tcl from /data to project dir now the ACE file was created properly for ML501 but it did also not work.

Ooopla the MDM FSL link option was not enabled in the hardware project, thats why. Adding FSL (this had to be done in MHS as the FSL bus was not visible in GUI) resynthesize, test - no luck either, the ERR2 LED doesnt go RED, but nothing works. Starting XMD (while FPGA is loaded from new bitstream via CF card), now XMD doesnt work - it almost freezes after saying that FSL debug link is available, and gives error stopping CPU when loading ELD files.

Ok, lets try the "golden" download.bit from the reference design. Making ACE file - nothing! Trying XMD, it fails to connect to MDM or see MicroBlaze in scan chain completly. Reloading the bootloader from CF card, starting XMD - failed? Trying again, failed. Must be cable driver stopped working. Switching cables from USB to Cable IV, trying.. works. Says Caches are enabled well in the reference design there are no caches. Loading u-boot with XMD, run - ERR2 is RED. Trying to download bitstream with XPS/impact loading u-boot.elf with XMD nothing. Hm, maybe the problem is with exceptions - I had enabled all of them, lets try disabling exceptions leaving barrel-shift and FSL debug link enabled.

Maybe the downbload.bit from orignal ref design /implementatio/ directory works? Lets see - Design loaded from SPI memory ? I must have messed up the mode switches. Yes so it was!

Ok, selecting ACE, selectin "my ace" still the RED ERR2 LED! Ok, P&R finished lets try, no RED LED, but no loaded designs work. And one timing constraint was not met.

Trying trying trying. Hm, lets start XMD from commandline not from GUI. Using bootloader design, u-boot works, loading my bitstream, u-boot works. Maybe the FSL link isnt working? Changing the tcl file back, regenerating ACE file (this takes now looong time) done!

Loading from my ACE file, RED LED, no uart activity. But what happened? The FPGA and DDR2 memory is now loaded with design that I compiled and with the last u-boot, ok, lets see starting XMD from commandline, looking at the u-boot base address looks ok, eg system ace software loading was succesful. Starting from u-boot base address (without reloading) and it works!

So the bitstream is OK, uboot is ok, the SW is loaded into memory but when loaded from compact flash doesnt autostart (or starts and stalls somewhere).

Power off, setting cfgaddr=6, power on, starting XMD looking at registers looks like the CPU isnt started at all, ah there was a warning about start address not being there in the ELF file! maybe I fixed it badly? But when loaded with XMD the same ELF file loads ok, and set start address also properly?

Oioiaai - I had the u-boot compiled to DDR2 memory base, and had the genace patched to that address, but later I had changed the uboot to load at different address so uclinux could be loaded at DDR2 base address but had not fixed the genace to reflect the new address.

Lets try maybe now the FSL loading also works, nops nothing. Back to the big ACE files without the use of fast FSL download link.

an NOW !!! u-boot works :) here is terminal log session:

****************************************************************************************

Welcome to the Xilinx Virtex-5 ML501 Evaluation Platform Bootloader Menu!

Please choose a demo by typing in the number of the demo you want to use

Or select a demo using the directional buttons and LCD or VGA display (Then press the center button to start the selected demo)

  1. Virtex-5 Slide Show
  2. Web Server Demo
  3. Simon Game
  4. Chipscope Pro Demo
  5. USB Demo
  6. My own ACE file
  7. Ring Tone Player Rebooting to System ACE Configuration Address 6... Using default environment

u-boot ML501 => ver

U-Boot 1.1.4 (Oct 17 2006 - 21:45:50) => help ? - alias for 'help' base - print or set address offset bootm - boot application image from memory cmp - memory compare cp - memory copy crc32 - checksum calculation echo - echo args to console fatinfo - print information about filesystem fatload - load binary file from a dos filesystem fatls - list files in a directory (default /) go - start application at address 'addr' help - print online help loads - load S-Record file over serial line loop - infinite loop on address range md - memory display mm - memory modify (auto-incrementing) mtest - simple RAM test mw - memory write (fill) nm - memory modify (constant address) printenv- print environment variables reset - Perform RESET of the CPU run - run commands in an environment variable setenv - set environment variables version - print monitor version =>bye!

Antti

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