xilinx power pc & microblaze

Hi,

take a look at

Shared Memory Multiprocessing Using the Virtex II PPC: Sharing Memory, Sharing a UART, and Synchronization A Guide for the XUP Development Board John K. Bennett1 University of Colorado at Boulder November 2005

Beside shared memory to connect two or more Microblaze cores you can use the FSL interface.

For example see

A MicroBlaze Based Multiprocessor SoC P.HUERTA, J.CASTILLO, J.I.MÁRTINEZ, V.LÓPEZ HW/SW Codesign Group Universidad Rey Juan Carlos

28933 Móstoles, Madrid SPAIN {pablo.huerta, javier.castillo, joseignacio.martinez, victor.lopez }@urjc.es

One obstacle is the limited support of the Xilinx EDK for multiple cores. You can add multiple cores and their peripherals to your EDK design but you have to craft the memory map by hand for example.

If you target Virtex-4 instead of Virtex-IIPro you can use the APU of the PPC core to connect PPC and Microblaze cores via an APU-FSL bridge. This has the advantage that the software for PPC and Microblaze can be quite similar.

In my opinion the main challenge is to build a software which makes efficient use of multiple cores. On-chip memory is quite limited if distributed among a number of cores. Depending on your application data distribution and scheduling can add quite an overhead so you might run out of on-chip memory.

Regards, Andreas