Field-Programmable Gate Arrays

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xilinx sync fifo with first word fall-through

I have to make a quick fix to get OPB_UARTLITE fifo larger seems like simple thing, just replace the fifo, but xilinx c...
6 comments posted 20yrs
posted by Antti.Lukats
6 comments posted 20yrs posted by Antti.Lukats

Am I seeing meta-stable or what?

It happens in a Virtex-E There's a 1M cycles test pattern on a 10 bit data bus with an ENABLE signal (high for 1 M cycl...
3 comments posted 20yrs
posted by ccon67
3 comments posted 20yrs posted by ccon67

can someone recommend a board?

Hi all, After some hardware problems with our protoype I have been advised to use a board. But I cannot find one with a...
7 comments posted 20yrs
posted by subhasri.krishnan
7 comments posted 20yrs posted by subhasri.krishnan

OT: FPGA soft-core humor

---------- Is an 8-bit soft-core CPU (e.g. picobalze(tm)), too big for your task? Is even a 4-bit CPU too much? Well at...
13 comments posted 20yrs
posted by vze24h5m
13 comments posted 20yrs posted by vze24h5m

Meta-stable problem with MAX-II ?

I'm trying to snag a 90nS pulse with a 16MHz clock. On paper, it should work just fine: 62.5 < 90. What I see is that i...
9 comments posted 20yrs
posted by ghelbig
9 comments posted 20yrs posted by ghelbig

Single Bank Vs Multiple Banks in sdram

Hi All, I was working with a design which stored data in a single bank in a memory and it worked just fine. Now I have...
5 comments posted 20yrs
posted by subhasri.krishnan
5 comments posted 20yrs posted by subhasri.krishnan

V5LXT support for ISE released yesterday

silently - but its really available for downloads. first you read 5 different answer records, then download 5 different...
2 comments posted 20yrs
posted by Antti.Lukats
2 comments posted 20yrs posted by Antti.Lukats

Xilinx MIG 1.6 doesn't launch

Hi there, I've recently installed the Xilinx ISE toolset so that I can play with the Memory Interface Generator. I foll...
6 comments posted 20yrs
posted by sjalloq
6 comments posted 20yrs posted by sjalloq

Supported bus widths for RLDRAM on Virtex4?

Hi there, I'm trying to decide on which FPGA vendor to use for a project out of Xilinx and Altera. The one we chose wil...
1 comments posted 20yrs
posted by sjalloq
1 comments posted 20yrs posted by sjalloq

Stream cipher

Hi, Can anyone suggest a good stream cipher algorithm for hardware implementation.
6 comments posted 20yrs
posted by jesuraj.vinoth
6 comments posted 20yrs posted by jesuraj.vinoth

Simple multiply in Xilinx?

In the following module, module mult (output reg[7:0] z, input [3:0] a); always @* begin z = a*a; end endmodule ModelSi...
4 comments posted 20yrs
posted by gspivey
4 comments posted 20yrs posted by gspivey

What should I do with std.textio.all of ModelSim

Hi, I have a problem with textio library while compiling a file using ModelSim. I have use the library: use std.textio....
13 comments posted 20yrs
posted by wtxwtx
13 comments posted 20yrs posted by wtxwtx