What should I do with std.textio.all of ModelSim

That line in the .MPF file is not quite the end of the story. If you have a file in your project list you can change the properties to have it compile using either '87, '93 or '02 which will override the default. Since that source file isn't typically in the list of files that you would normally compile it might be that this file got inadvertantly recompiled at some point using the '87 syntax.

Try dragging that source file over into the project workspace window and right click on it to manually change the property to be '93 syntax and recompile. After that you can remove the source from the workspace.

KJ

Hi KJ, Thank you very much.

What you said is what exactly I want.

Weng

Hi KJ, It is still problem !!!

I moved the textio.vhd to the top of my project window, compiled it with compilation property set at 1076-1993, everything worked well, but compiling other vhdl files still generated the following errors:

- Loading package vital_timing

-- Loading package textio

** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136) Unknown identifier "read_mode". ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112) FILE declaration was written using 1076-1993 syntax. Recompile using the -93 option. ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): VHDL Compiler exiting

It seems that the compiler went to "-- Loading package textio" that generated error information.

I recompiled the textio and got the information: # Compile of textio.vhd was successful.

Recompiling my vhdl files still generated the same error information as above.

What can I do to resolve the problem?

Thank you.

Weng

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Hi KJ, I know why your method doesn't work after reading the library contents:

1. My design module bram64_512 is to use Xilinx block ram that was generated by XilinxCore generator;
2. It has Library XilinxCoreLib that may need textio package;
3. When textio.vhd was deleted from package in library window, it reappeared in the library window again next time the bram64_512 module was compiled and still generated the same error information

** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136) Unknown identifier "read_mode". ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112) FILE declaration was written using 1076-1993 syntax. Recompile using the -93 option. ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): VHDL Compiler exiting

Thank you.

Weng

Maybe you have an old version of modelsim? Upgrade or read the manual.

-- Mike Treseler

Rebuilding Supplied Libraries Resource libraries are supplied precompiled in the modeltech installation directory. If you need to rebuild these libraries, the sources are provided in the vhdl_src directory; a macro file is also provided for Windows platforms (rebldlibs.do). To rebuild the libraries, invoke the DO file from within ModelSim with this command: do rbldlibs.do Make sure your current directory is the modeltech install directory before you run this file. Note Because accelerated subprograms require attributes that are available only under the 1993 standard, many of the libraries are built using vcom with the

-93 option. Shell scripts are provided for UNIX (rebuild_libs.csh and rebuild_libs.sh). To rebuild the libraries, execute one of the rebuild_libs scripts while in the modeltech directory.

Hi Mike and KJ, Thank you for your help.

I resolved the problem with a surprise method.

The method KJ suggested is 95% right, but I failed at the last step.

I copied textio.vhd into my project, compiled it and project still was wrong.

My son helped me. He tried and was successful.

What is the difference between my and his procedures?

I compiled textio.vhd file and compiled all files by clicked icons in manu: 'compile' and 'compile all'.

He compild textio.vhd using compile/compile-selected manus.

I don't understand two things:

1. Why textio.vhd suddenly does not work after it had worked for 3 months?
2. Why clicking compile/compile-selected manus works but clicking icon doesn't?

ModelSim really is a great software that makes everybody guess and confusing !!!

Weng

Sounds like your son got the compile order right and "compile all" didn't. Consider writing a .do file for this and run it from the command line: do compile.do

-- Mike Treseler

Hi Mike, It has nothing to do with compile order. My son is not an vhdl writer, but knows many thing unregular. He just happend to get the thing done right, many times I asked for his help and he got things done.

I tried following several options without success:

1. Put textio.vhd in the project top position;
2. Compile all by clicking manu icon;
3. Compile by clicking manu icon with textio.vhd selected;

My son put textio.vhd at the last position in project file list, select textio.vhd, then clicked manu compile/compile-selected and compiled textio.vhd only. After that he compiled all files and succeeded.

If the compile position is concerned, his position is wrong, because textio.vhd would be called before all files, but he did it.

Thank you.

Weng

Yes, your sun was just lucky. I don't use the Modelsim GUI for compilation because it doesn't always get it right and I can never tell exactly what it is doing.

My point was, that if you write a script, you are in control. It is a good idea to clean out the work directory each time as shown below because you can fool yourself with leftovers otherwise. Good luck

-- Mike Treseler _________________________________________________

#

set this uart set mydesign $this set mytb test_$this echo Assuming [pwd] is the right directory. vdel -all ;# clean last compilation vlib work vmap work work vcom $mydesign.vhd $mytb.vhd restart -f ;# so I can use this same script to rerun radix hex; ;# Make bus values easy to read add wave * ;# Signals add wave /$mytb/main/* ;# Test variables add wave /$mytb/dut/main/* ;# UUT variables run -all; # Make wave window readable WaveRestoreCursors {{Cursor 1} {194 ns} 0} configure wave -namecolwidth 277 WaveRestoreZoom {178 ns} {281 ns}

Based on what I've seen on this thread it appears to me that it probably does have to do with the compile order.

My earlier suggestion was a band-aid since it appeared that 'something' had recreated textio for you and done so using the wrong style ('87).

The problem though seems to have to do with the 'bram64_512' module that is in your current project since earlier in the thread you said that after deleting the textio from the library it reappeared after compiling 'bram64_512'. This would imply that 'bram64_512' is creating it's own version of the textio package that is at the root of what you're fighting.

The problem that you need to hunt down is what exactly what source file(s) in your project is(are) creating textio (and why?) and then why is it compiling it '87 syntax. The way to attack that is to clean textio out of the library and then compile each file in your project one at a time. Do this for each since for all you know textio might be in more than one of your source files. The other way would be to do a text search through each source file and find where the package is being created....but if the project list is relatively short, clicking to compile and then looking at the library result works too.

KJ

I have just added an item to my list of advantages to inferring block ram from a code template :)

-- Mike Treseler

Hi KJ, I have two files written by myself containing textio.vhd file.

All other blocks, like bram64_512 module, are generated by Xilinx CoreGenerator and their vhdl files don't contain explicitly 'std.textio.all;'

When I first changed my two files to include write() and writeline() functions, everything went well. Suddenly one day textio.vhd problem burst from blue.

Your suggestion is of valuable. My son finished the last touch to finish the job.

Thank you.

Weng

Hi Mike, How do you infer a block ram? I would like to learn the technique.

Thank you.

Weng