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Single Bank Vs Multiple Banks in sdram

Hi All, I was working with a design which stored data in a single bank in a memory and it worked just fine. Now I have moved my design to a chip with a smaller capacity (64Mb) so I need use multiple banks.

When I use banks 0 and 1 and try to display image from bank 0, the image from bank 1 is displayed. But if I use banks 0 and 2 or 0 and 3, and when i try to display from bank 0, the result is ok. Similarly if I use 2 and 3 , it doesnt work. But if I use 2 and 0 or 2 and 1 then it is ok. Has anyone had a similar problem before?

Thanks Subhasri

Reply to
Subhasri krishnan
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It seems too obvious, but are you sure you're actually driving the BA[0] address line? The symptoms look like the line isn't switching...

Reply to
Gabor

Yes I am pretty sure. I can see the lines switch in my post place and route simulation. I was just wondering..could this have anything to do with the refresh?

Reply to
Subhasri krishnan

Have you obtained a VHDL/Verilog model of the memory somewhere (even a similar memory, if you cannot find the exact one) and seen what happens in simulation?

Reply to
Duane Clark

i just checked my hardware and it looks like BA[0] isnt working. thanks for that suggestion.

Reply to
Subhasri krishnan

I just checked my hardware and BA[0] isnt working. Thanks for that suggestion. I always end up thinking that there is something wrong with my description.

Reply to
Subhasri krishnan

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