Latest threads in Field-Programmable Gate Arrays

Upgrading spartan-II: possible?

Hi everybody, I have a board with a spartan-II (xc2s200-5FG456) but I'm running out of area, I wonder if it's possible...

1 20yrs

25mV

1 20yrs 25mV

confused result in Logic Analyser, being crazy...

hi, I've have debugging this for the whole afternoonn today, can not get the problem away, becoming crazy..... I've 1....

3 20yrs

uvbaz

3 20yrs uvbaz

avalon tristate slave address

Hi, I try to connect my off-chip 16 bits wide SRAM to a Nios 2 system by using a tristate bus. In the documentation of...

0 20yrs

someone

0 20yrs someone

How to send data/program to the memory of a Spartan 3 starter kit board

Hi my friends, We know little about Spartan and Xilinx. We are connecting our Spartan 3 starter kit board to a PC and u...

8 20yrs

jiaojialin

8 20yrs jiaojialin

Microblaze FPU and IEEE754 single precision number format

Hi All, I started using a microblaze design that included the FPU. As a test that the FPU is working I created a small...

1 20yrs

acurtin

1 20yrs acurtin

How to generate a PROM file and then burn it on FPGA

Hi, I am using ML403 board with Virtex-4. I need to generate and download a PROM file into the PROM and then use it aft...

5 20yrs

sandip.gaikwad

5 20yrs sandip.gaikwad

How to simulate netlist with gated clock?

Hi all, When I simulate netlist with gated clock, I found the output is very different with what I see in RTL level. So...

9 20yrs

zhushenli

9 20yrs zhushenli

Should I use an external synthesis tool?

Hello all, I'm designing with Altera FPGA with their Quartus software. My company also have license for Mentor Graphics...

4 20yrs

avishorp

4 20yrs avishorp

Modelsim problem - mixed VHDL,Verilog & VHO

I'm having problems getting a simulation running. Here's the recipe... Quartus output VHO file - contains VHDL & Verilo...

6 20yrs

markm

6 20yrs markm

Chip to Chip LVDS

Hi i'm currently working on a high-speed chip-to-chip serial interface FPGA interface, i would like to know some sugges...

6 20yrs

yy7d6

6 20yrs yy7d6

XUP USB

I know there exists a path for the XUP board to communicate with a PC via the USB port because Chipscope does it and I...

2 20yrs

mdhicks2

2 20yrs mdhicks2

Once synthesized BRAMs are still vanishing in WebPACK version 8.1 and up (version 7 was working!)

Hello all, This is a repeat from article 104429 from june 17th to this group, see http://www.fpga-faq.com/archives/1044...

0 20yrs

sietse

0 20yrs sietse

ISE/EDK project on a file server?

Hi, I'm having problems hosting a ISE/EDK 8.1 SP3 project on a file server. The server runs Samba3 on Redhat. The works...

2 20yrs

jetmarc

2 20yrs jetmarc

surprised output of Xilinx Virtex-4

hallo everyone, I am here again, :) I have download my program to my Xilinx Virtex-4 FPGA, and connect the Oscilloscope...

7 20yrs

uvbaz

7 20yrs uvbaz

Cypress 68013 - Xilinx FPGA

Hi everyone, I am trying to add a USB 480Mbps interface to my fpga design which will stream data in one direction only...

5 20yrs

alastairlynch

5 20yrs alastairlynch

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