Field-Programmable Gate Arrays

confused result in Logic Analyser, being crazy...

hi, I've have debugging this for the whole afternoonn today, can not get the problem away, becoming crazy..... I've 1....

3 comments posted 19yrs

posted by uvbaz

3 comments posted 19yrs posted by uvbaz

avalon tristate slave address

Hi, I try to connect my off-chip 16 bits wide SRAM to a Nios 2 system by using a tristate bus. In the documentation of...

0 comments posted 19yrs

posted by someone

0 comments posted 19yrs posted by someone

How to send data/program to the memory of a Spartan 3 starter kit board

Hi my friends, We know little about Spartan and Xilinx. We are connecting our Spartan 3 starter kit board to a PC and u...

8 comments posted 19yrs

posted by jiaojialin

8 comments posted 19yrs posted by jiaojialin

Microblaze FPU and IEEE754 single precision number format

Hi All, I started using a microblaze design that included the FPU. As a test that the FPU is working I created a small...

1 comments posted 19yrs

posted by acurtin

1 comments posted 19yrs posted by acurtin

How to generate a PROM file and then burn it on FPGA

Hi, I am using ML403 board with Virtex-4. I need to generate and download a PROM file into the PROM and then use it aft...

5 comments posted 19yrs

posted by sandip.gaikwad

5 comments posted 19yrs posted by sandip.gaikwad

How to simulate netlist with gated clock?

Hi all, When I simulate netlist with gated clock, I found the output is very different with what I see in RTL level. So...

9 comments posted 19yrs

posted by zhushenli

9 comments posted 19yrs posted by zhushenli

Should I use an external synthesis tool?

Hello all, I'm designing with Altera FPGA with their Quartus software. My company also have license for Mentor Graphics...

4 comments posted 19yrs

posted by avishorp

4 comments posted 19yrs posted by avishorp

Modelsim problem - mixed VHDL,Verilog & VHO

I'm having problems getting a simulation running. Here's the recipe... Quartus output VHO file - contains VHDL & Verilo...

6 comments posted 19yrs

posted by markm

6 comments posted 19yrs posted by markm

Chip to Chip LVDS

Hi i'm currently working on a high-speed chip-to-chip serial interface FPGA interface, i would like to know some sugges...

6 comments posted 19yrs

posted by yy7d6

6 comments posted 19yrs posted by yy7d6

XUP USB

I know there exists a path for the XUP board to communicate with a PC via the USB port because Chipscope does it and I...

2 comments posted 19yrs

posted by mdhicks2

2 comments posted 19yrs posted by mdhicks2

Once synthesized BRAMs are still vanishing in WebPACK version 8.1 and up (version 7 was working!)

Hello all, This is a repeat from article 104429 from june 17th to this group, see http://www.fpga-faq.com/archives/1044...

0 comments posted 19yrs

posted by sietse

0 comments posted 19yrs posted by sietse

ISE/EDK project on a file server?

Hi, I'm having problems hosting a ISE/EDK 8.1 SP3 project on a file server. The server runs Samba3 on Redhat. The works...

2 comments posted 19yrs

posted by jetmarc

2 comments posted 19yrs posted by jetmarc

surprised output of Xilinx Virtex-4

hallo everyone, I am here again, :) I have download my program to my Xilinx Virtex-4 FPGA, and connect the Oscilloscope...

7 comments posted 19yrs

posted by uvbaz

7 comments posted 19yrs posted by uvbaz

Cypress 68013 - Xilinx FPGA

Hi everyone, I am trying to add a USB 480Mbps interface to my fpga design which will stream data in one direction only...

5 comments posted 19yrs

posted by alastairlynch

5 comments posted 19yrs posted by alastairlynch

Global Clocks in Xilinx Virtex-4

hallo everyone, I know that global clocks allow distributing the clock signal all over the FPGA with a low skew, but wh...

11 comments posted 19yrs

posted by uvbaz

11 comments posted 19yrs posted by uvbaz