confused result in Logic Analyser, being crazy...

Nov 07, 2006 3 Replies
U

hi,



I've have debugging this for the whole afternoonn today, can not get the problem away, becoming crazy.....



I've 1. writen a VHDL-Code for Serial-Parallel-Converter on the Virtex-4 FPGA(Both Pre-SImulation and Post-Simulation pass) 2. downloaded the file to the PROM 3. then feed the CLOCK signal, RESET signal and SERIAL input signal with the Agilent Logic Analyser onto the FPGA 4. and then feed the 16-bits PARALLEL OUTPUT signal and a OUTPUT CLOCK(16 times slowly as input clock) back to the LA.



However, there seems to be something wrong. The output did NOT equal the input.



What the LA send: rst_n clk_sd i_sd



1 0 0
1 1 0 ...
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S

I notice rst_n never resets!

Think sync

Slurp

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B

hi, as Slurp already mentioned, the reset seems to be missing, but besides that..

What about your Clock signal? Are there Overshots or Ground Bouncing at your FPGA Input? Depending on your measuring setup and the sensitivity of your LA-Pods these might be invisible to your LA, but valid for the Clock input of your FPGA. Since only the clock edge is of importance here and not the frequency it doesn't matter if you use 150 MHz or 1 MHz when you have this problem. It only depends on the rise time and drive strength of your Clock generator and the associated wire(transmission line) to your FPGA Input.

You need some good oszillscope to analyse this, and it may also happen that the problem vanishes when the oszilloscope is connected to your system. In that case the problem is there but can't be seen due to the influence of your probe (input impedance) which changes the behavior of your transmission line.

have a nice measuring Eilert

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U

Hi, Slurp, hi Backhus,

Thanks for your advise

I've found the problem: i feed the input singal through the Agilent Soft Touch Cable(E5404A), which contains a RC-Network inside. And that's why the output by 1MHz worse then by 150MHz, because of the character of this RC.

hmmm.....

Regards, Cheng

backhus schrieb:

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