Field-Programmable Gate Arrays

PCIe latency

Hi Im trying to design a high speed data capture card. Im using a Lattice ECP2M-50 FPGA with the one-board SERDES units...

2 comments posted 19yrs

posted by slkjas

2 comments posted 19yrs posted by slkjas

To Xilinx guys out there - microblaze mapping problem

Hi, I have a design in which I need to instantiate two microblaze system instances (the same microblaze system in two p...

6 comments posted 19yrs

posted by me_2003

6 comments posted 19yrs posted by me_2003

choise of fpga platform

Hello everyone, I need some help coising a platform to programm an fpga for my project. I need a fast fpga because the...

2 comments posted 19yrs

posted by tsemertzidis

2 comments posted 19yrs posted by tsemertzidis

Schifra Reed-Solomon ECC Library

Hi all, I'd like to announce that the open source Schifra C++ Reed-Solomon error correcting code library is now availab...

0 comments posted 19yrs

posted by partow

0 comments posted 19yrs posted by partow

I2C Master in Verilog

The opencores.org I2C appears to be only in VHDL. Does anyone know of a free I2C master in Verilog? Thanks, Chris.

2 comments posted 19yrs

posted by nospam

2 comments posted 19yrs posted by nospam

Formal Logic Equivalent Check (LEC)

Hi all, When do Formal Equivalent Check (RTL and Gate Level) , I remember that the tool compare the comb logic between...

2 comments posted 19yrs

posted by zhushenli

2 comments posted 19yrs posted by zhushenli

Spartan3E kit and BPI configuration problem.

Hi! There got to be a large number of owners of the $149 Spartan3E kit out there. I wonder if you have as little succes...

0 comments posted 19yrs

posted by jorgen.gade

0 comments posted 19yrs posted by jorgen.gade

post-synthesis simulation issues with ModelSim

Hi all again, I have a fairly straight forward systolic array design which uses the fixed_point type. It simulates fine...

3 comments posted 19yrs

posted by skatsev

3 comments posted 19yrs posted by skatsev

How to transform matlab value to FPGA value

I have implemented (-1,+1) boxed-constraint algorithm into FPGA desgin. The algorithm is to solve the equation Rh+n=b i...

0 comments posted 19yrs

posted by threeinchnail

0 comments posted 19yrs posted by threeinchnail

Integration of modules

Hi everybody, I have implemented a SDRAM Controller in Spartan 3s400.I already have another working core inside the sam...

4 comments posted 19yrs

posted by amirtham

4 comments posted 19yrs posted by amirtham

Using Altera Nios II Stratix II dev kit just as FPGA.

Hello. Got this board without any intention to use Nios, but just to use EP2S60 chip. Drawed very simple schematics, lo...

0 comments posted 19yrs

posted by drop669

0 comments posted 19yrs posted by drop669

FSL microblaze to co-processor write problem...

Hi guys, I'm trying to connect a simple co-processor to microblaze. The co-processor simply gets 8 inputs and does a si...

2 comments posted 19yrs

posted by amirhossein.gholamipour

2 comments posted 19yrs posted by amirhossein.gholamipour

PCI

May I connect 11 PCI cards (in each I use Xilinx FPGA) in one PCI bus, if use to generate IDSEL signals AD 12...AD31 lin...

3 comments posted 19yrs

posted by axalay

3 comments posted 19yrs posted by axalay

Cleaning generated files in Xilinx 8.2 EDK and ISE

Hi All, Does anyone know when I should "Clean all generated files" in Xilinx 8.2i EDK? Should it be done before or afte...

4 comments posted 19yrs

posted by james.h.w

4 comments posted 19yrs posted by james.h.w

EDK Modelsim Simulation with RS232 Hook

Hello all, Some time ago with an older version of the EDK (v6 I think) there was a ML300 design that would simulate the...

0 comments posted 19yrs

posted by anthony.j.mahar

0 comments posted 19yrs posted by anthony.j.mahar