Latest threads in Field-Programmable Gate Arrays

Division by a constant

So I just had a thought. Most synthesis tools (in VHDL, and I assume in Verilog) will allow you to use the division ope...

10 11yrs

rgaddi

10 11yrs rgaddi

Call for Participation: ACM/IEEE Symposium on Architectures for Networking and Communications Systems

>>> CALL FOR PARTICIPATION -- ANCS 2015 > CONFERENCE OVERVIEW > IMPORTANT DATES > HOTEL INFORMATION > CONFERENCE PROGRAM...

0 11yrs

erke9581

0 11yrs erke9581

Microblaze with AXI streaming interfaces

Hello, I am trying to connect my IP to the microblaze by AXI streaming protocol. I have connected my IP to the microbla...

0 11yrs

104923

0 11yrs 104923

Question about summation function

Hello! I've using VHDL for like 2 years or even more but just today i wonde? how it works. Summation function form any...

1 11yrs

1

1 11yrs 1

Graduate Research Assistantship at the Computer Systems Lab, College of Electronics and Information Engineering, Chosun University, Gwangju, Republic of Korea

Graduate Research Assistantship at the Computer Systems Lab, College of Ele ctronics and Information Engineering, Chosu...

0 11yrs

femiadeluyi

0 11yrs femiadeluyi

Does each core of 8-core Intel processor has an independent floating X87 unit?

Hi, Does each core of 8-core Intel processor has an independent floating X87 unit? Here are some texts from Intel lates...

1 11yrs

wtxwtx

1 11yrs wtxwtx

Bad condition in wait statement, or only one clock per process.

Hi, i am working on the following code but i have error as: "Bad condition in wait statement, or only one clock per pro...

1 11yrs

jagtapashwini08

1 11yrs jagtapashwini08

Interpret a VHDL statement within a serial to paralell port

First, thank you for taking the time to consider the questions I have not a nswered. I am working on a 32 bit serial to...

6 11yrs

cydrollinger

6 11yrs cydrollinger

Intel in Talks to buy Altera

http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172 --------------------------------------- Posted throu...

28 11yrs

1

28 11yrs 1

Pengadaan Pelatihan/Training PT MMS 2015

Training Syllabus: INDUSTRIAL TOXICOLOGY & HYGIENE MONIRORING (BASIC PRINCIPLES IN OCCUPATIONAL HYGIENE) Almost Running...

1 11yrs

bursatrainingbandung

1 11yrs bursatrainingbandung

Multicycle paths using clock enable (in Synplify Pro)

Hi all, I am looking for a generic set of TCL commands (for Synplify) to constrain _all_ flip-flops which are connected...

2 11yrs

karl-heinz.rossmann

2 11yrs karl-heinz.rossmann

Call for Posters: ACM/IEEE Symposium on Architectures for Networking and Communications Systems

CALL FOR POSTERS The 11th ACM/IEEE Symposium on Architectures for Networking and Communications Systems ANCS 2015 http:...

0 11yrs

erke9581

0 11yrs erke9581

code c of HM5883

good morning I want a code C for reading and writing of i2c for the HM5883 sensor. best regards ------------------------...

1 11yrs

103905

1 11yrs 103905

Lattice MachXO3L - new "F"sub-subfamily...

Lattice has shipped new version ov their Diamond tool v 3.4.1. for FPGA design. Changelog lists support for new MachXO3...

2 11yrs

brankob

2 11yrs brankob

Compiling Xilinx libraries for ModelSim PE 10.4 simulation out of ISE 8.2i

Simulation of your project written in ISE 8.2i, for those using old tools f or whatever reason, must first compile the...

0 11yrs

cydrollinger

0 11yrs cydrollinger

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