Latest threads in Field-Programmable Gate Arrays

Is it possible to have a parameterized verilog module name in verilog or systemverilog?

Hi, I am trying create verilog module that can support parameterized instance n ame. I understand that the signal width...

6 11yrs

cpandya

6 11yrs cpandya

[Call For Papers]: The 18th Conference on Reconfigurable Ubiquitous Computing, RUC'2015, Szczecin, Poland, Sep. 17 - 18, 2015

The 18th Conference on Reconfigurable Ubiquitous Computing, RUC?201 5 Szczecin, Poland, Sep. 17 - 18, 2015 Conference I...

0 11yrs

lukasz.mazurowski

0 11yrs lukasz.mazurowski

ESP8266 based Xilinx Virtual Cable server?

Hi, I often need to access the debugged FPGA boards remotely. Now when Xilinx has made its Xilinx Virtual Cable specifi...

1 11yrs

wzab

1 11yrs wzab

Oqpsk Demod

Hi all , I implement qpsk demodulator on National instruments Fpga . Now i want to Demodulate Oqpsk signal . As the dif...

1 11yrs

105327

1 11yrs 105327

IIR filter bus width

Hello! I'm having trouble with 4th order butterworth filter. I'm using two cascade biquads in direct form I because it...

1 11yrs

105368

1 11yrs 105368

Clock triggered FSM

Hello boys, I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to c...

3 11yrs

95179

3 11yrs 95179

16->5 "Sort"

I'm trying to design a circuit (Virtex-7) which you might call either a pri ority encoder or a sorter. This is what it...

23 11yrs

kevin.neilson

23 11yrs kevin.neilson

ZYNQ temperature

Does anyone know if the ZYNQ chips have an internal high-temperature shutdown? They are behaving like they do. -- John...

25 11yrs

jlarkin

25 11yrs jlarkin

Spartan-3 stater kit

Dear all, I'm really not a specialist in FPGA :-) For several years now I have a microbalze SoC running on a Digilent S...

9 11yrs

jmariano65

9 11yrs jmariano65

Interested in VHDL and FPGA Development?

Check out my course! Lifetime and Unlimited Access! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-in...

0 11yrs

jjchristman13

0 11yrs jjchristman13

Xilinx Aurora link splitter

Hi, I'm a software guy and now that I have a hardware problem, I hope to find some good advice here. There are two devi...

2 11yrs

hvdh

2 11yrs hvdh

Directly connect two XAUI ports inside FPGA

Hi all, to implement something like a passthru mode, we want to directly connect two XAUI ports inside the FPGA. The FP...

3 11yrs

g!!rw

3 11yrs g!!rw

Choosing the right FPGA board

Hello! I have several years of experience in programming, and I'd like to move on to FPGAs to enjoy more fun. As I have...

8 11yrs

105208

8 11yrs 105208

does anybody use systemc in FPGA flow?

Hi I just wanted to know if people use systemc in FPGA flow. systemc can be used for cycle accurate simulation, where i...

4 11yrs

93490

4 11yrs 93490

Aurora IP 8B10B problem with TVALID

I am getting unexpected SOF(AXI_OP_TVALID) signal down as shown in the figure (find the fig in attachments). I have tak...

0 11yrs

104867

0 11yrs 104867

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