Field-Programmable Gate Arrays

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ESP8266 based Xilinx Virtual Cable server?

Hi, I often need to access the debugged FPGA boards remotely. Now when Xilinx has made its Xilinx Virtual Cable specifi...
1 comments posted 11yrs
posted by wzab
1 comments posted 11yrs posted by wzab

Oqpsk Demod

Hi all , I implement qpsk demodulator on National instruments Fpga . Now i want to Demodulate Oqpsk signal . As the dif...
1 comments posted 11yrs
posted by 105327
1 comments posted 11yrs posted by 105327

IIR filter bus width

Hello! I'm having trouble with 4th order butterworth filter. I'm using two cascade biquads in direct form I because it...
1 comments posted 11yrs
posted by 105368
1 comments posted 11yrs posted by 105368

Clock triggered FSM

Hello boys, I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to c...
3 comments posted 11yrs
posted by 95179
3 comments posted 11yrs posted by 95179

16->5 "Sort"

I'm trying to design a circuit (Virtex-7) which you might call either a pri ority encoder or a sorter. This is what it...
23 comments posted 11yrs
posted by kevin.neilson
23 comments posted 11yrs posted by kevin.neilson

ZYNQ temperature

Does anyone know if the ZYNQ chips have an internal high-temperature shutdown? They are behaving like they do. -- John...
25 comments posted 11yrs
posted by jlarkin
25 comments posted 11yrs posted by jlarkin

Spartan-3 stater kit

Dear all, I'm really not a specialist in FPGA :-) For several years now I have a microbalze SoC running on a Digilent S...
9 comments posted 11yrs
posted by jmariano65
9 comments posted 11yrs posted by jmariano65

Interested in VHDL and FPGA Development?

Check out my course! Lifetime and Unlimited Access! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-in...
0 comments posted 11yrs
posted by jjchristman13
0 comments posted 11yrs posted by jjchristman13

Xilinx Aurora link splitter

Hi, I'm a software guy and now that I have a hardware problem, I hope to find some good advice here. There are two devi...
2 comments posted 11yrs
posted by hvdh
2 comments posted 11yrs posted by hvdh

Directly connect two XAUI ports inside FPGA

Hi all, to implement something like a passthru mode, we want to directly connect two XAUI ports inside the FPGA. The FP...
3 comments posted 11yrs
posted by g!!rw
3 comments posted 11yrs posted by g!!rw

Choosing the right FPGA board

Hello! I have several years of experience in programming, and I'd like to move on to FPGAs to enjoy more fun. As I have...
8 comments posted 11yrs
posted by 105208
8 comments posted 11yrs posted by 105208

does anybody use systemc in FPGA flow?

Hi I just wanted to know if people use systemc in FPGA flow. systemc can be used for cycle accurate simulation, where i...
4 comments posted 11yrs
posted by 93490
4 comments posted 11yrs posted by 93490

Aurora IP 8B10B problem with TVALID

I am getting unexpected SOF(AXI_OP_TVALID) signal down as shown in the figure (find the fig in attachments). I have tak...
0 comments posted 11yrs
posted by 104867
0 comments posted 11yrs posted by 104867

Division by a constant

So I just had a thought. Most synthesis tools (in VHDL, and I assume in Verilog) will allow you to use the division ope...
10 comments posted 11yrs
posted by rgaddi
10 comments posted 11yrs posted by rgaddi