Hi Jim, glen, JK, rickman, Mike, Andy,
I have filed a provisional patent application: "Systematic method of coding wave pipelined circuits in HDL". If it is proved correct, the patent will introduce 1 keyword, 3 permanent constants, 1 concurrent statement and four source code modules for a new library in HDL and thoroughly resolve a pend ing problem so that every digital designer can code wave-pipelined circuits in HDL.
Here is the abstract of the invention:
The present invention classifies all critical paths into two basic type s: a series critical path and a feedback critical path, and divides each of wave-pipelined circuits into two components: a static logic part, called c ritical path component (CPC), and a dynamic logic part, formalized into fou r wave-pipelining components (WPC) shared by all wave-pipelined circuits. E ach wave-pipelining ready code in HDL comprises two components: a WPC insta ntiation and a CPC instantiation wire-connected and linked by a new link st atement. Each WPC has new wave constants which play the same role as generi c constants do, but whose initial values are determined and assigned by a s ynthesizer after code analysis, so designers can use after-synthesization i nformation in their code before synthesization for wave-pipelining technolo gy. The responsibility of analyzing and manipulating wave-pipelining ready code, generating and implementing wave-pipelined circuits on a design-wide or chip-wide scale in HDL is shifted from designers to synthesizers.
Anyone who are interested in its content is welcome to send a email request to the following email address: wtx wtx @ gmail . com with title "Systemat ic" and he will receive the full documents: one specification, 9 drawings a nd one text file in VHDL.
If one reviews the files and feels that it would be a good thing to recomme nd the application to his company to buy it, the first person to do it afte r his recommended company does so will receive $10,000 commission fee.
All people who are interested in the topics are better to refer the same to pics in VHDL group, because its example source code is in VHDL and it canno t not be implemented in any FPGA chip.
Thank you.
Weng