Field-Programmable Gate Arrays

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DDS

What is the best way to implement a multi channel DDS. I need a DDS that has 8 channels that are time-multiplexed. I am...
10 comments posted 11yrs
posted by 4575
10 comments posted 11yrs posted by 4575

IIC in microblaze

hello I need your help please. I want to connect a gyrocompas(HMC5883L) with a microblaze which is done by I2c and as m...
8 comments posted 11yrs
posted by 103905
8 comments posted 11yrs posted by 103905

Program Xilinx with Altera JTAG Programmer?

Hello, I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG...
11 comments posted 11yrs
posted by jmm385
11 comments posted 11yrs posted by jmm385

Microblaze problem with FSL core

Hi guys, I'm not sure this is the right place to ask this question, but I found no answers to it on xilinx forums. Hope...
2 comments posted 11yrs
posted by 103842
2 comments posted 11yrs posted by 103842

An Altera CPLD "JTAG Unlocker"

Hi There, From time to time I see people having Altera CPLDs on the "JTAG Lockout" st atus. I have a few EPM7128s on th...
0 comments posted 11yrs
posted by marcelo.f.dantas
0 comments posted 11yrs posted by marcelo.f.dantas

FPGA Project -

Looking for someone to work on a project. Quick Notes 1. PCI FGPA Card (standard off the shelf is possible) 2. Interfac...
3 comments posted 11yrs
posted by joolzg
3 comments posted 11yrs posted by joolzg

Inferring F7 / F8 Mux in Xilinx

I'm posting this here for my own future reference. If you infer a mux with fewer than 2**n inputs, Vivado won't infer t...
2 comments posted 11yrs
posted by kevin.neilson
2 comments posted 11yrs posted by kevin.neilson

Kintex UltraScale board with two DDR4 interfaces?

Hello, I am looking for a Xilinx Kintex UltraScale FPGA board, where it would be possible to run two separated DDR4 con...
0 comments posted 11yrs
posted by 103481
0 comments posted 11yrs posted by 103481

Re: Open Source GPGPU core

I tried building your toolchain on both a 32 and 64 bit amd Ubuntu 14.10 system and get: Linking CXX shared library ../...
8 comments posted 11yrs
posted by 84408
8 comments posted 11yrs posted by 84408

processor core validation

Hi everyone, I was wondering if anyone can point me to some formal method to validate a soft processor core. We have th...
3 comments posted 11yrs
posted by al.basili
3 comments posted 11yrs posted by al.basili

Topics for Projects on FPGA+Computer Archtecture

Hi, I have to work on a project related to FPGA (Altera DEI or Altera DEII) and computer architecture. Can anyone sugge...
4 comments posted 11yrs
posted by vrbvasu
4 comments posted 11yrs posted by vrbvasu

data memory mapping microblaze

INFO: this very same post was posted to comp.arch.embedded with no follow up over few days, that's the reason why I dec...
5 comments posted 11yrs
posted by al.basili
5 comments posted 11yrs posted by al.basili