Latest threads in Field-Programmable Gate Arrays

Compiling Xilinx libraries for ModelSim PE 10.4 simulation out of ISE 8.2i

Simulation of your project written in ISE 8.2i, for those using old tools f or whatever reason, must first compile the...

0 11yrs

cydrollinger

0 11yrs cydrollinger

[JOB POSTING] Sought: Freelance FPGA PCB Designer

We are searching for a freelance PCB designer that is familiar with FPGA, D DR3, LVDS, SMPS, Analog-to-Digital converte...

0 11yrs

capossio.leonardo

0 11yrs capossio.leonardo

DDS

What is the best way to implement a multi channel DDS. I need a DDS that has 8 channels that are time-multiplexed. I am...

10 11yrs

4575

10 11yrs 4575

IIC in microblaze

hello I need your help please. I want to connect a gyrocompas(HMC5883L) with a microblaze which is done by I2c and as m...

8 11yrs

103905

8 11yrs 103905

Program Xilinx with Altera JTAG Programmer?

Hello, I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG...

11 11yrs

jmm385

11 11yrs jmm385

Microblaze problem with FSL core

Hi guys, I'm not sure this is the right place to ask this question, but I found no answers to it on xilinx forums. Hope...

2 11yrs

103842

2 11yrs 103842

An Altera CPLD "JTAG Unlocker"

Hi There, From time to time I see people having Altera CPLDs on the "JTAG Lockout" st atus. I have a few EPM7128s on th...

0 11yrs

marcelo.f.dantas

0 11yrs marcelo.f.dantas

New invention: Systematic method of coding wave pipelined circuits in HDL

Hi Jim, glen, JK, rickman, Mike, Andy, I have filed a provisional patent application: "Systematic method of coding wave...

2 11yrs

wtxwtx

2 11yrs wtxwtx

FPGA Project -

Looking for someone to work on a project. Quick Notes 1. PCI FGPA Card (standard off the shelf is possible) 2. Interfac...

3 11yrs

joolzg

3 11yrs joolzg

Inferring F7 / F8 Mux in Xilinx

I'm posting this here for my own future reference. If you infer a mux with fewer than 2**n inputs, Vivado won't infer t...

2 11yrs

kevin.neilson

2 11yrs kevin.neilson

Kintex UltraScale board with two DDR4 interfaces?

Hello, I am looking for a Xilinx Kintex UltraScale FPGA board, where it would be possible to run two separated DDR4 con...

0 11yrs

103481

0 11yrs 103481

Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea

The Embedded System on Chip Lab of the Hallym University seeks to recruit p romising PhD and MSc research students. The...

0 11yrs

jeonggun.Lee

0 11yrs jeonggun.Lee

Re: Open Source GPGPU core

I tried building your toolchain on both a 32 and 64 bit amd Ubuntu 14.10 system and get: Linking CXX shared library ../...

8 11yrs

84408

8 11yrs 84408

Re: Dynamic partial reconfiguration on Spartan 3 chips

yes i am in need of DPR on spartan 3,Can you help?

1 11yrs

niksharma291

1 11yrs niksharma291

processor core validation

Hi everyone, I was wondering if anyone can point me to some formal method to validate a soft processor core. We have th...

3 11yrs

al.basili

3 11yrs al.basili

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