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I2C "READ" Setup/Hold Requirement

Hello

For the I2C read, the step by step, the algorithm is:

1). write slave address+write bit 2). write register address 3). write slave addres+read bit 4). read

After the end of step 2, and before step 3, you need to set the STA to indicate the real read. Note that STA is indicated by transition of HIGH to LOW on the SDA while SCL remains HIGH. I am wondering if there is minimum wait time between step 2 and beginning of step 3?

Note that my design uses OpenCores' I2C (if it matters). Thanks.

Happy Turkey Day,

-M

Reply to
markus
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Hi,

I have been having fun with I2C for a while. If you read the I2C specs, you will see that the same delays come up everywhere for any given bus speed.

For 400kbps, this magic number is 600ns: SCL and SDA pulses must be

600ns wide minimum, a master should leave the bus idle for 600ns between transactions, SDA-to-SCL edges for start/stop should be at least 600ns apart, etc.

Since the condition between your #2 and #3 should be a 'restart', there should usually not be any extra delays needed there, other than the usual 600ns SDA-to-SCL for start/stop conditions. Then again, many I2C devices have quirks that must be dealt with on a case-by-case basis.

The > Hello

Reply to
Daniel S.

Thanks.

Your post definitely explains why I have problems (or no problems) with certain slaves.

Have a Great Thanksgiving!

Daniel S. wrote:

Reply to
markus

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