Spartan 3E-Kit

I found the thread about this kit but cannot write there, since it is more than 60 days old.

I am seeking for an empty or small project to start with the xilinx ide. Of course I found the sample projects, but a) they are too complex IMO (i do not need the pico blaze yet ) and b) I am having difficulties in creating a complete and working project from out of the given files.

To be honest, I am afraid of using a wrong configuration - esspeciall pin files - and then ruin my fpga!

So if anybody has an "empty" project with correct settings (like unused pins z) and /or "z" definitions for the board (i think it is something as an ucf) I was happy if he could send me that.

Thanks in advance

Reply to
spartanius
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You can copy the UCF definition from the PDF documentation and then set an option (I forget which) in the IDE to ignore unconnected pins.

Not empty, but you can delete anything you don't need:

formatting link

Included on the web page: the non-intuitve steps required to synthesize it, starting and use of iMPACT :-)

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

thanks, but the synthesis sais "NgdBuild:755 - Line 7 in 'E:/xilinxprojekte/frankbuss/src/spartan3e.ucf':" for nearly all the lines up to 200x. (?

Reply to
spartanius

I also got there very elaborated messages on my design today. After digging some time, I realized, that nets "LOC"ed in the UCF did not exist in the HDL sources or had typing errors. But why the hell doesn't the error message tell that?

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

I can't reproduce this with the ise\Spartan3E.ise project file. If you've setup your own project, right-click on "Implement Design"->"Translate" and enable "Allow Unmatched LOC Constraints", if it is Uwe referenced. Do you use the latest version of ISE (help->about: 8.2.0.3i) ?

Another interesting source of errors: ISE saves local settings for your projects in C:\Documents and Settings\YourName\Local Settings\Temp\something-with-ise-and-your-project-name Once I replaced the source files for my project, because I didn't want to setup all the settings again, but it didn't worked until I deleted the temporary files.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

I am currently using the ISE 8.1 - you seem to use 8.2. Could this be the explanation for the errors?

Anyway, I installed the newest available version now, and still have no success. rightclicking the *.ise opens the ISE, but I have no sources and have to add them manually again like before.

It seems to be a challenge to get a Xilinx Environment run. (?) Well, when starting with Altera`s, 2 years ago, everything worked fine the first run (eval board board, first project, quartus ide etc).

Hm....

Maybe I am a bit to lazy, or missed something important, or I am simply to strong on the Altera line to switch easily.

In any case I am a bit disappointed, that there are no simple and working examples in a -> starter kit.

Anybody else working with this kit ?

Reply to
spartanius

I got the kit and just started modifying the existing demo. The unused pins that aren't included in the top level or .ucf don't cause me any problems. Heck, I even expanded upon the PicoBlaze code to do my own LCD stuff. It was quite a nice experience.

I have the full .ucf if/when I need to add signals in my HDL and current .ucf. I used it in 8.1 and 8.2, various service packs.

I liked the kit so much I got the 1600E version, too.

- John_H

Reply to
John_H

Using 8.1 can't be the explanation, because you have updated to 8.2. I can start the project with double click.

Maybe someone from Xilinx can help? Looks like you can't have anything: With Quartus you have a nice and clean IDE (ok, sometimes switching to the programmer after synthesizing doesn't update to the last synthesized program and minor other bugs, but at least the GUI looks and feels more modern), but you can't trust the synthesizer until some service packs were released and with ISE webpack the backend may be more stable, but using the IDE is a nightmare sometimes.

BTW: in German Windows, deleting "C:\Dokumente und Einstellungen\YourName\Lokale Einstellungen\Temp\xil*" may help.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

I only find "C:\Dokumente und Einstellungen\MyName" but there is no "Lokale Einstellungen", however, neiter with the user "administrator" nor with "all users". ????

Reply to
spartanius

You have to enable hidden files. In German Windows just enable the well hidden option "Extras->Ordernoptionen->Ansicht->Versteckte Dateien und Ordner->Alle Dateien und Ordner anzeigen" (and while you are in this mask, make sure to disable the option "Erweiterungen bei bekannten Dateitypen ausblenden" for a better life :-)

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

of course I did all this but something must have gone wrong though. Anyway I got it now , found the xil... directories and deleted them. There are 3!! options now in XP to prevent files from beeing shown (american programming logic :x) But now let`s step away from this windows issue ...

I again unpacked the rar to the root directory, double clicked the ise, but still have now hdls. the project only shows "spartan 3e" and "xa2c*.**". No "test" or anyting like that.

Anybody has a 100% worling example?

Reply to
spartanius

What good does it do you if we have working examples?

Right out of the box, it worked.

Right out of the box, I could modify the starter kit design and it worked.

How can my having an example that works - the one that ships with the box - possibly help you in your situation?

You have the same tools and same files at your disposal.

Reply to
John_H

John_H schrieb:

What I basically wanted to learn from a working project, is the correct project tree including pinout/ucf, constraints and such things. It is easier to start from that point rather than doing everything from scratch.

You surely mean the s3eskstart? I wonder why there is no *.ise file included. (How did the creator handle the project?)

---

Anyway, I do not want to start with THIS particular design, but have a starting point for every design, i will create with this board. Therefore, I need the correct project settings for this FPGA and a pin definition of 100% coverage for the particular wiring of this board, switching off inactive functions explicitely.

Searching the docs of the starter kit, I found and example ucf. According to my understanding, it seems to cover all available pins and functions (?). What I now need , is a hdl-design acting as the toplevel. Can this be created automatically from out of the ucf?

Reply to
spartanius

The documentation shows that the needed files are s3esk_startup.vhd control.vhd kcpsm3.vhd and s3esk_startup.ucf

where you need to download the free PicoBlaze cores as well (kcpsm3.vhd).

Create a new project. Specify VHDL flow. Choose the XC3S500E-4FG320. Add the VHDL files to the project. Add the .ucf to the project. And implement.

The .ise file tends to be a very large binary file that doesn't zip well and you need to be at least familiar enough with the tools to take the first step of creating the project or the rest of the journey will not go very well.

The reference design is found at

formatting link

and includes the s3esk_startup_rev2.pdf file for quick instructions including where to find picoblaze.

I don't have ISE installed on my home system at the moment. If you can't even get to where the project can synthesize, let us know. It should be quick.

Reply to
John_H

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